51 lines
1.4 KiB
Python
51 lines
1.4 KiB
Python
from migen import *
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from migen.build.platforms.sinara import kasli, efc
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from sync_serdes import MultiLineTX
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from bidirectionalIO import BiDirectionalIO
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from eem_helpers import generate_pads
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from kasli_crg import TransceiverCRG
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class ShortPulseTX(Module):
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def __init__(self, i_pads, o_pads):
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# TX serdes
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self.submodules.tx = MultiLineTX()
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# TX PHY
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self.submodules.channel = BiDirectionalIO(i_pads, o_pads)
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self.comb += [
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# Transmitter to SERDES
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self.channel.i.eq(self.tx.ser_out),
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self.channel.t.eq(self.tx.t_out),
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# # SERDES to receiver
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# self.rx.ser_in_no_dly.eq(self.channel.o),
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# Hardwire TX with 1 pulse signal
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self.tx.txdata.eq(0b00000000000000010000)
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]
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if __name__ == "__main__":
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platform = efc.Platform()
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# Generate pads for the I/O blocks
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for eem in range(2):
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generate_pads(platform, eem)
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data_eem = 0
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i_pads = [
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platform.request("dio{}".format(data_eem), i) for i in range(4)
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]
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o_pads = [
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platform.request("dio{}".format(data_eem), i+4) for i in range(4)
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]
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crg = TransceiverCRG(platform, platform.request("gtp_clk"))
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top = ShortPulseTX(i_pads, o_pads)
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top.submodules += crg
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output_dir = "{}_{}_build".format("efc", "master")
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platform.build(top, build_dir=output_dir)
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