256 lines
7.7 KiB
Python
256 lines
7.7 KiB
Python
from migen import *
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from migen.genlib.fifo import SyncFIFO
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from migen.genlib.misc import WaitTimer
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from migen.build.platforms.sinara import kasli, efc
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from eem_helpers import generate_pads
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from serdes_comm import BiDirectionalIO
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from sync_serdes import SingleLineRX, BitSlipReader, SlaveAligner
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from uart_log import UARTLogger
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from kasli_crg import TransceiverCRG
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class SingleLineReader(Module):
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def __init__(self, uart_log, i_pads, o_pads):
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# UART Logger
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self.submodules.uart_logger = uart_log
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# Recorder
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self.submodules.rx_buffer = SyncFIFO(10, 64)
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# PHY Channel
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self.submodules.channel = BiDirectionalIO(i_pads, o_pads)
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# Single line RX SERDES
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self.submodules.rx = SingleLineRX()
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# bitslip reader
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self.submodules.bitslip_reader = BitSlipReader()
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self.submodules.postslip_reader = BitSlipReader()
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# Alignment modules
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self.submodules.slave_aligner = SlaveAligner()
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# Connect SERDES to PHY
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self.comb += [
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self.rx.ser_in_no_dly.eq(self.channel.o[0]),
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]
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# Debugging logics
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self.comb += [
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self.bitslip_reader.loopback_rxdata.eq(self.rx.rxdata),
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self.postslip_reader.loopback_rxdata.eq(self.rx.rxdata),
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self.slave_aligner.loopback_rxdata.eq(self.rx.rxdata),
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self.rx.master_bitslip.eq(
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self.bitslip_reader.bitslip
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| self.slave_aligner.master_bitslip
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| self.postslip_reader.bitslip
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),
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self.rx.slave_bitslip.eq(
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self.bitslip_reader.bitslip
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| self.slave_aligner.master_bitslip
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| self.postslip_reader.bitslip
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),
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]
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bitslip_count = Signal(3)
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fsm = FSM(reset_state="WAIT_DONE")
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self.submodules += fsm
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fsm.act("WAIT_DONE",
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self.bitslip_reader.start.eq(1),
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If(self.bitslip_reader.done,
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NextValue(bitslip_count, 0),
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NextState("WRITE_UPPER"),
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),
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)
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fsm.act("WRITE_UPPER",
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If(bitslip_count == 5,
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NextState("WAIT_BITSLIP_ALIGNED"),
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).Elif(self.uart_logger.tx_fifo.writable,
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self.uart_logger.tx_fifo.we.eq(1),
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self.uart_logger.tx_fifo.din.eq(self.bitslip_reader.data_result[bitslip_count][8:]),
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NextState("WRITE_LOWER"),
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),
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)
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fsm.act("WRITE_LOWER",
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If(self.uart_logger.tx_fifo.writable,
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self.uart_logger.tx_fifo.we.eq(1),
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self.uart_logger.tx_fifo.din.eq(self.bitslip_reader.data_result[bitslip_count][:8]),
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NextValue(bitslip_count, bitslip_count + 1),
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NextState("WRITE_UPPER"),
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)
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)
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fsm.act("WAIT_BITSLIP_ALIGNED",
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self.slave_aligner.start.eq(1),
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If(self.slave_aligner.done,
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NextState("BARRIER_UPPER"),
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),
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)
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fsm.act("BARRIER_UPPER",
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If(self.uart_logger.tx_fifo.writable,
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self.uart_logger.tx_fifo.we.eq(1),
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self.uart_logger.tx_fifo.din.eq(0xFF),
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NextState("BARRIER_LOWER"),
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),
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)
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fsm.act("BARRIER_LOWER",
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If(self.uart_logger.tx_fifo.writable,
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self.uart_logger.tx_fifo.we.eq(1),
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self.uart_logger.tx_fifo.din.eq(0xFF),
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NextState("REWAIT_BITSLIP_READ_DONE"),
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),
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)
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fsm.act("REWAIT_BITSLIP_READ_DONE",
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self.postslip_reader.start.eq(1),
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If(self.postslip_reader.done,
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NextValue(bitslip_count, 0),
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NextState("REWRITE_UPPER"),
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),
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)
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fsm.act("REWRITE_UPPER",
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If(bitslip_count == 5,
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NextState("TERMINATE"),
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).Elif(self.uart_logger.tx_fifo.writable,
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self.uart_logger.tx_fifo.we.eq(1),
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self.uart_logger.tx_fifo.din.eq(self.postslip_reader.data_result[bitslip_count][8:]),
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NextState("REWRITE_LOWER"),
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),
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)
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fsm.act("REWRITE_LOWER",
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If(self.uart_logger.tx_fifo.writable,
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self.uart_logger.tx_fifo.we.eq(1),
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self.uart_logger.tx_fifo.din.eq(self.postslip_reader.data_result[bitslip_count][:8]),
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NextValue(bitslip_count, bitslip_count + 1),
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NextState("REWRITE_UPPER"),
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)
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)
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fsm.act("TERMINATE",
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NextState("TERMINATE"),
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)
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# self.submodules.wait_timer = WaitTimer(127)
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# shift_count = Signal(5)
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# self.submodules.fsm = FSM(reset_state="WAIT")
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# self.fsm.act("WAIT",
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# self.wait_timer.wait.eq(1),
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# If(shift_count == 10,
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# NextState("DUMP_UPPER"),
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# ).Elif(self.wait_timer.done,
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# NextState("MEASURE"),
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# ),
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# )
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# self.fsm.act("MEASURE",
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# If(self.rx_buffer.writable,
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# self.rx_buffer.we.eq(1),
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# self.rx_buffer.din.eq(self.rx.rxdata),
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# NextState("SHIFT1"),
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# ),
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# )
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# self.fsm.act("SHIFT1",
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# self.rx.master_bitslip.eq(1),
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# self.rx.slave_bitslip.eq(1),
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# NextState("GAP"),
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# )
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# self.fsm.act("GAP",
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# NextState("SHIFT2"),
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# )
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# self.fsm.act("SHIFT2",
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# self.rx.master_bitslip.eq(1),
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# self.rx.slave_bitslip.eq(1),
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# NextValue(shift_count, shift_count + 1),
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# NextState("WAIT"),
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# )
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# self.fsm.act("DUMP_UPPER",
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# If(self.rx_buffer.readable,
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# If(self.uart_logger.tx_fifo.writable,
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# self.uart_logger.tx_fifo.we.eq(1),
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# self.uart_logger.tx_fifo.din.eq(self.rx_buffer.dout[8:]),
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# NextState("DUMP_LOWER"),
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# ),
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# ).Else(
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# NextState("TERMINATE"),
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# )
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# )
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# self.fsm.act("DUMP_LOWER",
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# If(self.uart_logger.tx_fifo.writable,
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# self.uart_logger.tx_fifo.we.eq(1),
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# self.uart_logger.tx_fifo.din.eq(self.rx_buffer.dout[:8]),
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# self.rx_buffer.re.eq(1),
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# NextState("DUMP_UPPER"),
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# ),
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# )
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# self.fsm.act("TERMINATE",
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# NextState("TERMINATE"),
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# )
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if __name__ == "__main__":
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import argparse
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import functools
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import os
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parser = argparse.ArgumentParser()
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parser.add_argument("platform")
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args = parser.parse_args()
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platform_dict = {
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"kasli": kasli.Platform(hw_rev="v2.0"),
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"efc": efc.Platform(),
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}
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sysclk_name = {
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"kasli": "clk125_gtp",
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"efc": "gtp_clk",
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}
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platform = platform_dict[args.platform]
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sysclk = platform.request(sysclk_name[args.platform])
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# Generate pads for the I/O blocks
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for eem in range(2):
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generate_pads(platform, eem)
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data_eem = 0
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i_pads = [
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platform.request("dio{}".format(data_eem), i) for i in range(4)
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]
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o_pads = [
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platform.request("dio{}".format(data_eem), i+4) for i in range(4)
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]
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crg = TransceiverCRG(platform, sysclk)
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uart_logger = UARTLogger(crg.sys_clk_freq)
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top = SingleLineReader(uart_logger, i_pads, o_pads)
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# Wire up UART core to the pads
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uart_pads = platform.request("serial")
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top.comb += [
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uart_logger.uart_rx.eq(uart_pads.rx),
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uart_pads.tx.eq(uart_logger.uart_tx),
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]
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top.submodules += crg
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output_dir = "{}_{}_build".format(args.platform, "satellite")
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platform.build(top, build_dir=output_dir)
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