from migen import *
from migen.build.platforms.sinara import kasli
from migen.genlib.fifo import SyncFIFO
from uart import UART
from kasli_crg import KasliCRG


class UARTLoopBack(Module):
    def __init__(self, sys_clk_freq):
        self.uart_rx = Signal()
        self.uart_tx = Signal()

        self.submodules.uart = UART(round((115200/sys_clk_freq)*2**32))
        self.comb += [
            self.uart.phy_rx.eq(self.uart_rx),
            self.uart_tx.eq(self.uart.phy_tx),
        ]

        # Attach buffer between UART RX --> TX
        # This constitutes the loopback channel
        self.submodules.buffer = SyncFIFO(8, 64)
        self.comb += [
            self.buffer.din.eq(self.uart.rx_data),
            self.buffer.we.eq(self.uart.rx_stb),
            self.uart.tx_data.eq(self.buffer.dout),
            self.uart.tx_stb.eq(self.buffer.readable),
            self.buffer.re.eq(self.uart.tx_ack),
        ]


if __name__ == "__main__":
    platform = kasli.Platform(hw_rev="v2.0")
    crg = KasliCRG(platform)
    top = UARTLoopBack(crg.sys_clk_freq)

    # Wire up UART core to the pads
    uart_pads = platform.request("serial")
    top.comb += [
        top.uart_rx.eq(uart_pads.rx),
        uart_pads.tx.eq(top.uart_tx),
    ]

    top.submodules += crg
    platform.build(top)