from migen import *
from migen.genlib.fifo import SyncFIFO


class Buffer(Module):
    def __init__(self, width=8, depth=128):
        self.din = Signal(width)
        self.i_stb = Signal()

        self.dout = Signal(width)
        self.o_stb = Signal()
        self.o_ack = Signal()

        # Underlying data structure
        self.submodules.fifo = SyncFIFO(width, depth)

        self.comb += [
            # TX path
            self.o_stb.eq(self.fifo.readable),
            self.dout.eq(self.fifo.dout),
            self.fifo.re.eq(self.o_ack),

            # RX path
            self.fifo.we.eq(self.i_stb),
            self.fifo.din.eq(self.din),
        ]