From e6902d1da596626915e6d2615628bb44e93ccc04 Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Mon, 24 Apr 2023 07:10:18 +0800
Subject: [PATCH] adjust register-wide bitslip right after slave bitslip

---
 sync_serdes.py | 41 ++++++++++++++++++++++++++++++++++++++---
 1 file changed, 38 insertions(+), 3 deletions(-)

diff --git a/sync_serdes.py b/sync_serdes.py
index 2d347b2..b4eee35 100644
--- a/sync_serdes.py
+++ b/sync_serdes.py
@@ -264,7 +264,7 @@ class SlaveAligner(Module):
             self.master_bitslip.eq(1),
             self.slave_bitslip.eq(1),
             If(self.slip_count == 5,
-                NextState("TERMINATE"),
+                NextState("SHIFT_WAIT_TIMER"),
             ).Else(
                 NextState("WAIT_TIMER"),
             )
@@ -277,7 +277,7 @@ class SlaveAligner(Module):
         fsm.act("CHECK_MASTER_BITSLIP",
             # At any point if the odd and/or even bits from the master reads 0
             # It implies the detuning is completed
-            NextState("TERMINATE"),
+            NextState("SHIFT_WAIT_TIMER"),
             If(check_odd & (odd_master_rxdata != 0),
                 NextState("MASTER_HIGH_BITSLIP_FIRST"),
             ),
@@ -308,13 +308,48 @@ class SlaveAligner(Module):
             )
         )
 
+        # After eliminating the potentially duplicating pattern,
+        # Shift the entire output pattern for delay tap optimization
+        # Ideally, the optimized first edge would be the middle pair
+        # So, shift it until bit 4/5 is set and bit 6 is not set
+        fsm.act("SHIFT_WAIT_TIMER",
+            self.stab_timer.wait.eq(1),
+            If(self.stab_timer.done,
+                NextState("SHIFT_SAMPLE_PATTERN"),
+            )
+        )
+
+        fsm.act("SHIFT_SAMPLE_PATTERN",
+            If((self.loopback_rxdata[4:6] != 0) & ~self.loopback_rxdata[6],
+                NextState("TERMINATE"),
+            ).Else(
+                NextState("SHIFT_HIGH_BITSLIP_FIRST"),
+            )
+        )
+
+        fsm.act("SHIFT_HIGH_BITSLIP_FIRST",
+            self.master_bitslip.eq(1),
+            self.slave_bitslip.eq(1),
+            NextState("SHIFT_LOW_BITSLIP"),
+        )
+
+        fsm.act("SHIFT_LOW_BITSLIP",
+            # bitslip signal is auto-reset
+            NextState("SHIFT_HIGH_BITSLIP_SECOND"),
+        )
+
+        fsm.act("SHIFT_HIGH_BITSLIP_SECOND",
+            self.master_bitslip.eq(1),
+            self.slave_bitslip.eq(1),
+            NextState("SHIFT_WAIT_TIMER")
+        )
+
         fsm.act("TERMINATE",
             self.done.eq(1),
             NextState("TERMINATE"),
         )
 
 
-
 class PhaseReader(Module):
     def __init__(self):
         # Drive IDELAYE2 CE pin to increment delay