load optimal delay tap
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@ -78,14 +78,8 @@ class SingleSerDesLoopBack(Module):
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self.phase_reader.delay_tap.eq(self.rx.cnt_out),
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self.phase_reader.delay_tap.eq(self.rx.cnt_out),
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self.delay_solver.delay_tap.eq(self.rx.cnt_out),
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self.delay_solver.delay_tap.eq(self.rx.cnt_out),
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# Increment control enable, such that phase_reader can
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# IDELAY delay tap control, such that phase_reader can
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# increment tap value after delay measurement
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# change tap value after delay measurement
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# Re-assign the incremnet control to the optimizer after the optimizer has started
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# If(self.delay_optimizer.start,
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# self.rx.ce.eq(self.delay_optimizer.inc_en),
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# ).Else(
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# self.rx.ce.eq(self.phase_reader.inc_en),
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# )
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self.rx.ce.eq(
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self.rx.ce.eq(
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self.phase_reader.inc_en |
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self.phase_reader.inc_en |
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self.delay_solver.inc_en
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self.delay_solver.inc_en
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@ -100,6 +94,8 @@ class SingleSerDesLoopBack(Module):
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self.slave_aligner.slave_bitslip |
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self.slave_aligner.slave_bitslip |
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self.post_align_reader.bitslip
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self.post_align_reader.bitslip
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),
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),
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self.rx.ld.eq(self.delay_solver.ld),
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self.rx.cnt_in.eq(self.delay_solver.opt_delay_tap),
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]
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]
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# Show measured result on UART
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# Show measured result on UART
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@ -271,10 +267,26 @@ class SingleSerDesLoopBack(Module):
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If(self.tx_fifo.writable,
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.delay_solver.opt_delay_tap),
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self.tx_fifo.din.eq(self.delay_solver.opt_delay_tap),
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NextState("TERMINATE"),
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NextState("RESAMPLE_RXDATA_UPPER"),
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),
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),
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)
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)
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fsm.act("RESAMPLE_RXDATA_UPPER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.rx.rxdata[8:]),
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NextState("RESAMPLE_RXDATA_LOWER"),
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)
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)
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fsm.act("RESAMPLE_RXDATA_LOWER",
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If(self.tx_fifo.writable,
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self.tx_fifo.we.eq(1),
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self.tx_fifo.din.eq(self.rx.rxdata[:8]),
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NextState("TERMINATE"),
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)
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)
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fsm.act("TERMINATE",
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fsm.act("TERMINATE",
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NextState("TERMINATE"),
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NextState("TERMINATE"),
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)
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)
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@ -32,7 +32,9 @@ class SingleLineRX(Module):
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def __init__(self):
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def __init__(self):
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self.rxdata = Signal(10)
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self.rxdata = Signal(10)
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self.ser_in_no_dly = Signal()
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self.ser_in_no_dly = Signal()
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self.ld = Signal()
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self.ce = Signal()
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self.ce = Signal()
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self.cnt_in = Signal(5)
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self.cnt_out = Signal(5)
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self.cnt_out = Signal(5)
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self.opt_delay = Signal(5)
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self.opt_delay = Signal(5)
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self.master_bitslip = Signal()
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self.master_bitslip = Signal()
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@ -97,21 +99,22 @@ class SingleLineRX(Module):
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# REFCLK refers to the clock source of IDELAYCTRL
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# REFCLK refers to the clock source of IDELAYCTRL
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p_REFCLK_FREQUENCY=200.0,
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p_REFCLK_FREQUENCY=200.0,
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p_PIPE_SEL="FALSE",
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p_PIPE_SEL="FALSE",
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p_IDELAY_TYPE="VARIABLE",
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p_IDELAY_TYPE="VAR_LOAD",
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p_IDELAY_VALUE=0,
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p_IDELAY_VALUE=0,
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i_C=ClockSignal("rx_sys"),
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i_C=ClockSignal("rx_sys"),
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# i_LD=self._dly_sel.storage[i//8] & self._rdly_dq_rst.re,
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i_LD=self.ld,
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# i_CE=self._dly_sel.storage[i//8] & self._rdly_dq_inc.re,
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i_CE=self.ce,
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i_LD=0,
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i_CE=self.ce, # TODO: Port output
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i_LDPIPEEN=0,
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i_LDPIPEEN=0,
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i_INC=1, # Always increment
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i_INC=1, # Always increment
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# Allow aligner to check delay tap value
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# Set the optimal delay tap via the aligner
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i_CNTVALUEIN=self.cnt_in,
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# Allow the aligner to check the tap value
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o_CNTVALUEOUT=self.cnt_out,
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o_CNTVALUEOUT=self.cnt_out,
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i_IDATAIN=self.ser_in_no_dly, o_DATAOUT=ser_in
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i_IDATAIN=self.ser_in_no_dly,
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o_DATAOUT=ser_in
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),
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),
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# IDELAYCTRL is with the clocking
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# IDELAYCTRL is with the clocking
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@ -434,6 +437,7 @@ class DelayOptimizer(Module):
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# OUT
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# OUT
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# Signal for controlling the channel delay tap
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# Signal for controlling the channel delay tap
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self.ld = Signal()
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self.inc_en = Signal()
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self.inc_en = Signal()
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# OUT
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# OUT
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@ -528,7 +532,7 @@ class DelayOptimizer(Module):
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fsm.act("SAMPLE_PULSE_OUT",
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fsm.act("SAMPLE_PULSE_OUT",
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If(~self.rxdata_array[self.expected_pulse],
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If(~self.rxdata_array[self.expected_pulse],
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NextValue(self.opt_delay_tap, self.min_delay + (self.max_offset >> 1)),
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NextValue(self.opt_delay_tap, self.min_delay + (self.max_offset >> 1)),
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NextState("TERMINATE"),
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NextState("LOAD_OPT_DELAY"),
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).Else(
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).Else(
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NextValue(self.max_offset, self.max_offset + 1),
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NextValue(self.max_offset, self.max_offset + 1),
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NextState("INC_PULSE_DELAY_OUT"),
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NextState("INC_PULSE_DELAY_OUT"),
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@ -541,6 +545,12 @@ class DelayOptimizer(Module):
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NextState("WAIT_PULSE_OUT"),
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NextState("WAIT_PULSE_OUT"),
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)
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)
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fsm.act("LOAD_OPT_DELAY",
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self.ld.eq(1),
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# The optimal delay tap is prepared in the SAMPLE_PULSE_OUT state
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NextState("TERMINATE"),
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)
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fsm.act("TERMINATE",
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fsm.act("TERMINATE",
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self.done.eq(1),
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self.done.eq(1),
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NextState("TERMINATE"),
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NextState("TERMINATE"),
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