diff --git a/multi_serdes_channel.py b/multi_serdes_channel.py index 3bdda41..c0f84ea 100644 --- a/multi_serdes_channel.py +++ b/multi_serdes_channel.py @@ -55,6 +55,9 @@ class MultiTransceiverChannel(Module): self.uart.tx_data.eq(self.tx_fifo.dout), self.uart.tx_stb.eq(self.tx_fifo.readable), self.tx_fifo.re.eq(self.uart.tx_ack), + + # Immediate start RX alignment procedure + self.rx.start.eq(1), ] rx_fsm = FSM(reset_state="WAIT_GROUP_ALIGN") diff --git a/multi_serdes_loopback.py b/multi_serdes_loopback.py index 8c1f56c..3753dbd 100644 --- a/multi_serdes_loopback.py +++ b/multi_serdes_loopback.py @@ -43,6 +43,9 @@ class MultiSerDesLoopBack(Module): self.uart.tx_data.eq(self.tx_fifo.dout), self.uart.tx_stb.eq(self.tx_fifo.readable), self.tx_fifo.re.eq(self.uart.tx_ack), + + # Just start RX alignment, no reason to wait + self.rx.start.eq(1), ] self.submodules.rx_fsm = FSM(reset_state="WAIT_GROUP_ALIGN") diff --git a/sync_serdes.py b/sync_serdes.py index e5b6501..1325d20 100644 --- a/sync_serdes.py +++ b/sync_serdes.py @@ -570,6 +570,8 @@ class SyncSingleRX(Module): # Ports # IN: Undelayed serial signal self.ser_in_no_dly = Signal() + # IN: Start RX alignment signal + self.start = Signal() # OUT: Received data after self-alignment, decimation self.rxdata = Signal(5) # OUT: RXDATA from this channel is self-aligned @@ -620,7 +622,7 @@ class SyncSingleRX(Module): self.submodules.fsm = FSM(reset_state="WAIT_SIGNAL") self.fsm.act("WAIT_SIGNAL", - If(self.rx.rxdata != 0, + If((self.rx.rxdata != 0) & self.start, NextState("WAIT_ALIGNER") ), ) @@ -673,6 +675,8 @@ class MultiLineRX(Module): # Ports # IN: Undelayed serial signal self.ser_in_no_dly = Signal(4) + # IN: Start alignment process of all channels + self.start = Signal() # OUT: Received data after self-alignment, decimation self.rxdata = Signal(20) # OUT: RXDATA from all channels are self-aligned @@ -693,8 +697,9 @@ class MultiLineRX(Module): self.comb += [ single_rx.ser_in_no_dly.eq(self.ser_in_no_dly[idx]), - # self.rxdata[5*idx:5*(idx+1)].eq(single_rx.rxdata), channel_align_done[idx].eq(single_rx.align_done), + # Propagate start alignment signal to all channels + single_rx.start.eq(self.start), ] # FIFOs for handling group delay