forked from M-Labs/artiq
Robert Jordens
307cd07b9d
tested/validated: * servo enable/disable * dds interface, timing, io_update, mask_nu * channel control (en_out, en_iir, profile) * profile configuration (coefficients, delays, offsets, channel) * adc timings and waveforms measured * asf state readback * adc readback individual changes below: suservo: correct rtio readback suservo: example, device_db [wip] suservo: change rtio channel layout suservo: mem ports in rio domain suservo: sck clocked from rio_phy suservo: cleanup, straighten out timing suservo: dds cs polarity suservo: simplify pipeline suservo: drop unused eem names suservo: decouple adc SR from IIR suservo: expand coredevice layer suservo: start the correct stage suservo: actually load ctrl suservo: refactor/tweak adc timing suservo: implement cpld and dds init
44 lines
1.3 KiB
Python
44 lines
1.3 KiB
Python
import logging
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from migen import *
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from . import spi
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logger = logging.getLogger(__name__)
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DDSParams = spi.SPIParams
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class DDS(spi.SPISimple):
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"""Multi-DDS SPI interface.
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* Supports SPI DDS chips like the AD9910.
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* Shifts data out to multiple DDS in parallel with a shared CLK and shared
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CS_N line.
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* Supports a single hardcoded command.
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* Configuration and setup must be done over a different channel.
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* Asserts IO_UPDATE for one clock cycle immediately after the SPI transfer.
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"""
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def __init__(self, pads, params):
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super().__init__(pads, params)
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self.profile = [Signal(32 + 16 + 16, reset_less=True)
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for i in range(params.channels)]
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cmd = Signal(8, reset=0x0e) # write to single tone profile 0
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assert params.width == len(cmd) + len(self.profile[0])
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self.sync += [
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If(self.start,
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[d.eq(Cat(p, cmd))
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for d, p in zip(self.data, self.profile)]
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)
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]
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# this assumes that the cycle time (1/125 MHz = 8 ns) is >1 SYNC_CLK
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# cycle (1/250 MHz = 4ns)
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done_old = Signal()
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self.sync += done_old.eq(self.done)
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self.comb += pads.io_update.eq(self.done & ~done_old)
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