forked from M-Labs/artiq
539 lines
19 KiB
Rust
539 lines
19 KiB
Rust
use board_misoc::{csr, clock};
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mod i2c {
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use board_misoc::{csr, clock};
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#[derive(Debug, Clone, Copy)]
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pub enum Dcxo {
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Main,
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Helper
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}
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fn half_period() { clock::spin_us(1) }
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const SDA_MASK: u8 = 2;
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const SCL_MASK: u8 = 1;
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fn sda_i(dcxo: Dcxo) -> bool {
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let reg = match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_in_read() },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_in_read() },
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};
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reg & SDA_MASK != 0
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}
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fn sda_oe(dcxo: Dcxo, oe: bool) {
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let reg = match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_oe_read() },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_oe_read() },
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};
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let reg = if oe { reg | SDA_MASK } else { reg & !SDA_MASK };
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match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_oe_write(reg) },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_oe_write(reg) }
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}
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}
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fn sda_o(dcxo: Dcxo, o: bool) {
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let reg = match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_out_read() },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_out_read() },
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};
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let reg = if o { reg | SDA_MASK } else { reg & !SDA_MASK };
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match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_out_write(reg) },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_out_write(reg) }
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}
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}
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fn scl_oe(dcxo: Dcxo, oe: bool) {
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let reg = match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_oe_read() },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_oe_read() },
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};
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let reg = if oe { reg | SCL_MASK } else { reg & !SCL_MASK };
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match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_oe_write(reg) },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_oe_write(reg) }
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}
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}
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fn scl_o(dcxo: Dcxo, o: bool) {
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let reg = match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_out_read() },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_out_read() },
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};
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let reg = if o { reg | SCL_MASK } else { reg & !SCL_MASK };
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match dcxo {
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Dcxo::Main => unsafe { csr::wrpll::main_dcxo_gpio_out_write(reg) },
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Dcxo::Helper => unsafe { csr::wrpll::helper_dcxo_gpio_out_write(reg) }
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}
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}
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pub fn init(dcxo: Dcxo) -> Result<(), &'static str> {
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// Set SCL as output, and high level
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scl_o(dcxo, true);
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scl_oe(dcxo, true);
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// Prepare a zero level on SDA so that sda_oe pulls it down
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sda_o(dcxo, false);
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// Release SDA
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sda_oe(dcxo, false);
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// Check the I2C bus is ready
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half_period();
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half_period();
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if !sda_i(dcxo) {
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// Try toggling SCL a few times
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for _bit in 0..8 {
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scl_o(dcxo, false);
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half_period();
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scl_o(dcxo, true);
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half_period();
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}
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}
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if !sda_i(dcxo) {
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return Err("SDA is stuck low and doesn't get unstuck");
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}
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Ok(())
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}
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pub fn start(dcxo: Dcxo) {
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// Set SCL high then SDA low
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scl_o(dcxo, true);
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half_period();
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sda_oe(dcxo, true);
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half_period();
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}
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pub fn stop(dcxo: Dcxo) {
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// First, make sure SCL is low, so that the target releases the SDA line
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scl_o(dcxo, false);
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half_period();
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// Set SCL high then SDA high
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sda_oe(dcxo, true);
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scl_o(dcxo, true);
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half_period();
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sda_oe(dcxo, false);
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half_period();
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}
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pub fn write(dcxo: Dcxo, data: u8) -> bool {
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// MSB first
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for bit in (0..8).rev() {
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// Set SCL low and set our bit on SDA
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scl_o(dcxo, false);
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sda_oe(dcxo, data & (1 << bit) == 0);
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half_period();
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// Set SCL high ; data is shifted on the rising edge of SCL
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scl_o(dcxo, true);
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half_period();
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}
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// Check ack
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// Set SCL low, then release SDA so that the I2C target can respond
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scl_o(dcxo, false);
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half_period();
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sda_oe(dcxo, false);
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// Set SCL high and check for ack
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scl_o(dcxo, true);
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half_period();
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// returns true if acked (I2C target pulled SDA low)
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!sda_i(dcxo)
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}
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pub fn read(dcxo: Dcxo, ack: bool) -> u8 {
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// Set SCL low first, otherwise setting SDA as input may cause a transition
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// on SDA with SCL high which will be interpreted as START/STOP condition.
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scl_o(dcxo, false);
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half_period(); // make sure SCL has settled low
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sda_oe(dcxo, false);
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let mut data: u8 = 0;
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// MSB first
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for bit in (0..8).rev() {
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scl_o(dcxo, false);
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half_period();
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// Set SCL high and shift data
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scl_o(dcxo, true);
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half_period();
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if sda_i(dcxo) { data |= 1 << bit }
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}
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// Send ack
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// Set SCL low and pull SDA low when acking
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scl_o(dcxo, false);
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if ack { sda_oe(dcxo, true) }
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half_period();
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// then set SCL high
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scl_o(dcxo, true);
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half_period();
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data
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}
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}
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mod si549 {
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use board_misoc::clock;
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use super::i2c;
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#[cfg(any(soc_platform = "metlino", soc_platform = "sayma_amc", soc_platform = "sayma_rtm"))]
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pub const ADDRESS: u8 = 0x55;
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#[cfg(soc_platform = "kasli")]
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pub const ADDRESS: u8 = 0x67;
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pub fn write(dcxo: i2c::Dcxo, reg: u8, val: u8) -> Result<(), &'static str> {
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i2c::start(dcxo);
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if !i2c::write(dcxo, ADDRESS << 1) {
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return Err("Si549 failed to ack write address")
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}
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if !i2c::write(dcxo, reg) {
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return Err("Si549 failed to ack register")
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}
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if !i2c::write(dcxo, val) {
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return Err("Si549 failed to ack value")
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}
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i2c::stop(dcxo);
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Ok(())
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}
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pub fn write_no_ack_value(dcxo: i2c::Dcxo, reg: u8, val: u8) -> Result<(), &'static str> {
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i2c::start(dcxo);
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if !i2c::write(dcxo, ADDRESS << 1) {
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return Err("Si549 failed to ack write address")
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}
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if !i2c::write(dcxo, reg) {
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return Err("Si549 failed to ack register")
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}
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i2c::write(dcxo, val);
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i2c::stop(dcxo);
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Ok(())
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}
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pub fn read(dcxo: i2c::Dcxo, reg: u8) -> Result<u8, &'static str> {
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i2c::start(dcxo);
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if !i2c::write(dcxo, ADDRESS << 1) {
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return Err("Si549 failed to ack write address")
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}
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if !i2c::write(dcxo, reg) {
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return Err("Si549 failed to ack register")
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}
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i2c::stop(dcxo);
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i2c::start(dcxo);
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if !i2c::write(dcxo, (ADDRESS << 1) | 1) {
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return Err("Si549 failed to ack read address")
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}
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let val = i2c::read(dcxo, false);
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i2c::stop(dcxo);
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Ok(val)
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}
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pub fn program(dcxo: i2c::Dcxo, hsdiv: u16, lsdiv: u8, fbdiv: u64) -> Result<(), &'static str> {
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i2c::init(dcxo)?;
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write(dcxo, 255, 0x00)?; // PAGE
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write_no_ack_value(dcxo, 7, 0x80)?; // RESET
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clock::spin_us(100_000); // required? not specified in datasheet.
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write(dcxo, 255, 0x00)?; // PAGE
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write(dcxo, 69, 0x00)?; // Disable FCAL override.
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// Note: Value 0x00 from Table 5.6 is inconsistent with Table 5.7,
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// which shows bit 0 as reserved and =1.
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write(dcxo, 17, 0x00)?; // Synchronously disable output
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// The Si549 has no ID register, so we check that it responds correctly
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// by writing values to a RAM-like register and reading them back.
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for test_value in 0..255 {
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write(dcxo, 23, test_value)?;
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let readback = read(dcxo, 23)?;
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if readback != test_value {
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return Err("Si549 detection failed");
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}
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}
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write(dcxo, 23, hsdiv as u8)?;
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write(dcxo, 24, (hsdiv >> 8) as u8 | (lsdiv << 4))?;
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write(dcxo, 26, fbdiv as u8)?;
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write(dcxo, 27, (fbdiv >> 8) as u8)?;
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write(dcxo, 28, (fbdiv >> 16) as u8)?;
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write(dcxo, 29, (fbdiv >> 24) as u8)?;
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write(dcxo, 30, (fbdiv >> 32) as u8)?;
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write(dcxo, 31, (fbdiv >> 40) as u8)?;
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write(dcxo, 7, 0x08)?; // Start FCAL
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write(dcxo, 17, 0x01)?; // Synchronously enable output
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Ok(())
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}
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// Si549 digital frequency trim ("all-digital PLL" register)
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// ∆ f_out = adpll * 0.0001164e-6 (0.1164 ppb/lsb)
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// max trim range is +- 950 ppm
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pub fn set_adpll(dcxo: i2c::Dcxo, adpll: i32) -> Result<(), &'static str> {
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write(dcxo, 231, adpll as u8)?;
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write(dcxo, 232, (adpll >> 8) as u8)?;
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write(dcxo, 233, (adpll >> 16) as u8)?;
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clock::spin_us(100);
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Ok(())
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}
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pub fn get_adpll(dcxo: i2c::Dcxo) -> Result<i32, &'static str> {
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let b1 = read(dcxo, 231)? as i32;
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let b2 = read(dcxo, 232)? as i32;
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let b3 = read(dcxo, 233)? as i8 as i32;
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Ok(b3 << 16 | b2 << 8 | b1)
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}
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}
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// to do: load from gateware config
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const DDMTD_COUNTER_N: u32 = 15;
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const DDMTD_COUNTER_M: u32 = (1 << DDMTD_COUNTER_N);
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const F_SYS: f64 = csr::CONFIG_CLOCK_FREQUENCY as f64;
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const F_MAIN: f64 = 125.0e6;
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const F_HELPER: f64 = F_MAIN * DDMTD_COUNTER_M as f64 / (DDMTD_COUNTER_M + 1) as f64;
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const F_BEAT: f64 = F_MAIN - F_HELPER;
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const TIME_STEP: f32 = 1./F_BEAT as f32;
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fn ddmtd_tag_to_s(mu: f32) -> f32 {
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return (mu as f32)*TIME_STEP;
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}
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fn get_frequencies() -> (u32, u32, u32) {
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unsafe {
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csr::wrpll::frequency_counter_update_en_write(1);
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// wait for at least one full update cycle (> 2 timer periods)
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clock::spin_us(200_000);
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csr::wrpll::frequency_counter_update_en_write(0);
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let helper = csr::wrpll::frequency_counter_counter_helper_read();
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let main = csr::wrpll::frequency_counter_counter_rtio_read();
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let cdr = csr::wrpll::frequency_counter_counter_rtio_rx0_read();
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(helper, main, cdr)
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}
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}
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fn log_frequencies() -> (u32, u32, u32) {
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let (f_helper, f_main, f_cdr) = get_frequencies();
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let conv_khz = |f| 4*(f as u64)*(csr::CONFIG_CLOCK_FREQUENCY as u64)/(1000*(1 << 23));
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info!("helper clock frequency: {}kHz ({})", conv_khz(f_helper), f_helper);
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info!("main clock frequency: {}kHz ({})", conv_khz(f_main), f_main);
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info!("CDR clock frequency: {}kHz ({})", conv_khz(f_cdr), f_cdr);
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(f_helper, f_main, f_cdr)
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}
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fn get_tags() -> (i32, i32, u16, u16) {
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unsafe {
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csr::wrpll::tag_arm_write(1);
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while csr::wrpll::tag_arm_read() != 0 {}
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let main_diff = csr::wrpll::main_diff_tag_read() as i32;
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let helper_diff = csr::wrpll::helper_diff_tag_read() as i32;
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let ref_tag = csr::wrpll::ref_tag_read();
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let main_tag = csr::wrpll::main_tag_read();
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(main_diff, helper_diff, ref_tag, main_tag)
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}
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}
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fn print_tags() {
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const NUM_TAGS: usize = 30;
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let mut main_diffs = [0; NUM_TAGS]; // input to main loop filter
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let mut helper_diffs = [0; NUM_TAGS]; // input to helper loop filter
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let mut ref_tags = [0; NUM_TAGS];
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let mut main_tags = [0; NUM_TAGS];
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let mut jitter = [0 as f32; NUM_TAGS];
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for i in 0..NUM_TAGS {
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let (main_diff, helper_diff, ref_tag, main_tag) = get_tags();
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main_diffs[i] = main_diff;
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helper_diffs[i] = helper_diff;
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ref_tags[i] = ref_tag;
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main_tags[i] = main_tag;
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}
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info!("DDMTD ref tags: {:?}", ref_tags);
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info!("DDMTD main tags: {:?}", main_tags);
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info!("DDMTD main diffs: {:?}", main_diffs);
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info!("DDMTD helper diffs: {:?}", helper_diffs);
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// look at the difference between the main DCXO and reference...
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let t0 = main_diffs[0];
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main_diffs.iter_mut().for_each(|x| *x -= t0);
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// crude estimate of the max difference across our sample set (assumes no unwrapping issues...)
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let delta = main_diffs[main_diffs.len()-1] as f32 / (main_diffs.len()-1) as f32;
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info!("detla: {:?} tags", delta);
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let delta_f: f32 = delta/DDMTD_COUNTER_M as f32 * F_BEAT as f32;
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info!("MAIN <-> ref frequency difference: {:?} Hz ({:?} ppm)", delta_f, delta_f/F_HELPER as f32 * 1e6);
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jitter.iter_mut().enumerate().for_each(|(i, x)| *x = main_diffs[i] as f32 - delta*(i as f32));
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info!("jitter: {:?} tags", jitter);
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let var = jitter.iter().map(|x| x*x).fold(0 as f32, |acc, x| acc + x as f32) / NUM_TAGS as f32;
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info!("variance: {:?} tags^2", var);
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}
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pub fn init() {
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info!("initializing WR PLL...");
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unsafe { csr::wrpll::helper_reset_write(1); }
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unsafe {
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csr::wrpll::helper_dcxo_i2c_address_write(si549::ADDRESS);
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csr::wrpll::main_dcxo_i2c_address_write(si549::ADDRESS);
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}
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#[cfg(rtio_frequency = "125.0")]
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let (h_hsdiv, h_lsdiv, h_fbdiv) = (0x05c, 0, 0x04b5badb98a);
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#[cfg(rtio_frequency = "125.0")]
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let (m_hsdiv, m_lsdiv, m_fbdiv) = (0x05c, 0, 0x04b5c447213);
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si549::program(i2c::Dcxo::Main, m_hsdiv, m_lsdiv, m_fbdiv)
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.expect("cannot initialize main Si549");
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si549::program(i2c::Dcxo::Helper, h_hsdiv, h_lsdiv, h_fbdiv)
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.expect("cannot initialize helper Si549");
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// Si549 Settling Time for Large Frequency Change.
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// Datasheet said 10ms but it lied.
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clock::spin_us(50_000);
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unsafe { csr::wrpll::helper_reset_write(0); }
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clock::spin_us(1);
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}
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pub fn diagnostics() {
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info!("WRPLL diagnostics...");
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info!("Untrimmed oscillator frequencies:");
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log_frequencies();
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info!("Increase helper DCXO frequency by +10ppm (1.25kHz):");
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si549::set_adpll(i2c::Dcxo::Helper, 85911).expect("ADPLL write failed");
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// to do: add check on frequency?
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log_frequencies();
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}
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fn trim_dcxos(f_helper: u32, f_main: u32, f_cdr: u32) -> Result<(i32, i32), &'static str> {
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info!("Trimming oscillator frequencies...");
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const DCXO_STEP: i64 = (1.0e6/0.0001164) as i64;
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const ADPLL_MAX: i64 = (950.0/0.0001164) as i64;
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const TIMER_WIDTH: u32 = 23;
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const COUNTER_DIV: u32 = 2;
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// how many counts we expect to measure
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const SYS_COUNTS: i64 = (1 << (TIMER_WIDTH - COUNTER_DIV)) as i64;
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const EXP_MAIN_COUNTS: i64 = ((SYS_COUNTS as f64) * (F_MAIN/F_SYS)) as i64;
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const EXP_HELPER_COUNTS: i64 = ((SYS_COUNTS as f64) * (F_HELPER/F_SYS)) as i64;
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// calibrate the SYS clock to the CDR clock and correct the measured counts
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// assume frequency errors are small so we can make an additive correction
|
|
// positive error means sys clock is too fast
|
|
let sys_err: i64 = EXP_MAIN_COUNTS - (f_cdr as i64);
|
|
let main_err: i64 = EXP_MAIN_COUNTS - (f_main as i64) - sys_err;
|
|
let helper_err: i64 = EXP_HELPER_COUNTS - (f_helper as i64) - sys_err;
|
|
|
|
info!("sys count err {}", sys_err);
|
|
info!("main counts err {}", main_err);
|
|
info!("helper counts err {}", helper_err);
|
|
|
|
// calculate required adjustment to the ADPLL register see
|
|
// https://www.silabs.com/documents/public/data-sheets/si549-datasheet.pdf
|
|
// section 5.6
|
|
let helper_adpll: i64 = helper_err*DCXO_STEP/EXP_HELPER_COUNTS;
|
|
let main_adpll: i64 = main_err*DCXO_STEP/EXP_MAIN_COUNTS;
|
|
if helper_adpll.abs() > ADPLL_MAX {
|
|
return Err("helper DCXO offset too large");
|
|
}
|
|
if main_adpll.abs() > ADPLL_MAX {
|
|
return Err("main DCXO offset too large");
|
|
}
|
|
|
|
info!("ADPLL offsets: helper={} main={}", helper_adpll, main_adpll);
|
|
Ok((helper_adpll as i32, main_adpll as i32))
|
|
}
|
|
|
|
fn statistics(data: &[u16]) -> (f32, f32) {
|
|
let sum = data.iter().fold(0 as u32, |acc, x| acc + *x as u32);
|
|
let mean = sum as f32 / data.len() as f32;
|
|
|
|
let squared_sum = data.iter().fold(0 as u32, |acc, x| acc + (*x as u32).pow(2));
|
|
let variance = (squared_sum as f32 / data.len() as f32) - mean;
|
|
return (mean, variance)
|
|
}
|
|
|
|
fn select_recovered_clock_int(rc: bool) -> Result<(), &'static str> {
|
|
info!("Untrimmed oscillator frequencies:");
|
|
let (f_helper, f_main, f_cdr) = log_frequencies();
|
|
if rc {
|
|
let (helper_adpll, main_adpll) = trim_dcxos(f_helper, f_main, f_cdr)?;
|
|
// to do: add assertion on max frequency shift here?
|
|
si549::set_adpll(i2c::Dcxo::Helper, helper_adpll).expect("ADPLL write failed");
|
|
si549::set_adpll(i2c::Dcxo::Main, main_adpll).expect("ADPLL write failed");
|
|
|
|
log_frequencies();
|
|
clock::spin_us(100_000); // TO DO: remove/reduce!
|
|
print_tags();
|
|
|
|
info!("increasing main DCXO by 1ppm (125Hz):");
|
|
si549::set_adpll(i2c::Dcxo::Main, main_adpll + 8591).expect("ADPLL write failed");
|
|
clock::spin_us(100_000);
|
|
print_tags();
|
|
|
|
si549::set_adpll(i2c::Dcxo::Main, main_adpll).expect("ADPLL write failed");
|
|
|
|
unsafe {
|
|
csr::wrpll::adpll_offset_helper_write(helper_adpll as u32);
|
|
csr::wrpll::adpll_offset_main_write(main_adpll as u32);
|
|
csr::wrpll::helper_dcxo_gpio_enable_write(0);
|
|
csr::wrpll::main_dcxo_gpio_enable_write(0);
|
|
csr::wrpll::helper_dcxo_errors_write(0xff);
|
|
csr::wrpll::main_dcxo_errors_write(0xff);
|
|
csr::wrpll::collector_reset_write(0);
|
|
}
|
|
clock::spin_us(1_000); // wait for the collector to produce meaningful output
|
|
unsafe {
|
|
csr::wrpll::filter_reset_write(0);
|
|
}
|
|
|
|
clock::spin_us(100_000);
|
|
|
|
print_tags();
|
|
// let mut tags = [0; 10];
|
|
// for i in 0..tags.len() {
|
|
// tags[i] = get_ddmtd_helper_tag();
|
|
// }
|
|
// info!("DDMTD helper tags: {:?}", tags);
|
|
|
|
unsafe {
|
|
csr::wrpll::filter_reset_write(1);
|
|
csr::wrpll::collector_reset_write(1);
|
|
}
|
|
clock::spin_us(50_000);
|
|
unsafe {
|
|
csr::wrpll::helper_dcxo_gpio_enable_write(1);
|
|
csr::wrpll::main_dcxo_gpio_enable_write(1);
|
|
}
|
|
unsafe {
|
|
info!("error {} {}",
|
|
csr::wrpll::helper_dcxo_errors_read(),
|
|
csr::wrpll::main_dcxo_errors_read());
|
|
}
|
|
info!("new ADPLL: {} {}",
|
|
si549::get_adpll(i2c::Dcxo::Helper)?,
|
|
si549::get_adpll(i2c::Dcxo::Main)?);
|
|
} else {
|
|
si549::set_adpll(i2c::Dcxo::Helper, 0).expect("ADPLL write failed");
|
|
si549::set_adpll(i2c::Dcxo::Main, 0).expect("ADPLL write failed");
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
pub fn select_recovered_clock(rc: bool) {
|
|
if rc {
|
|
info!("switching to recovered clock");
|
|
} else {
|
|
info!("switching to local XO clock");
|
|
}
|
|
match select_recovered_clock_int(rc) {
|
|
Ok(()) => info!("clock transition completed"),
|
|
Err(e) => error!("clock transition failed: {}", e)
|
|
}
|
|
}
|