forked from M-Labs/artiq
Sebastien Bourdeauducq
b10d3ee4b4
Kasli no longer has an internal RTIO clock. Switching clocks dynamically is no longer supported.
558 lines
20 KiB
Python
Executable File
558 lines
20 KiB
Python
Executable File
#!/usr/bin/env python3
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen.build.generic_platform import *
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from migen.build.xilinx.vivado import XilinxVivadoToolchain
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from migen.build.xilinx.ise import XilinxISEToolchain
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from misoc.interconnect.csr import *
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from misoc.cores import gpio, timer
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from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio, nist_clock, nist_qc2
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from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
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dds, spi2, ad53xx_monitor)
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from artiq.build_soc import build_artiq_soc
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from artiq import __version__ as artiq_version
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class _RTIOCRG(Module, AutoCSR):
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def __init__(self, platform, rtio_internal_clk, use_sma=True):
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self._clock_sel = CSRStorage()
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self._pll_reset = CSRStorage(reset=1)
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self._pll_locked = CSRStatus()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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# 100 MHz when using 125MHz input
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self.clock_domains.cd_ext_clkout = ClockDomain(reset_less=True)
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platform.add_period_constraint(self.cd_ext_clkout.clk, 5.0)
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if use_sma:
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ext_clkout = platform.request("user_sma_gpio_p_33")
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self.sync.ext_clkout += ext_clkout.eq(~ext_clkout)
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rtio_external_clk = Signal()
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if use_sma:
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user_sma_clock = platform.request("user_sma_clock")
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platform.add_period_constraint(user_sma_clock.p, 8.0)
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self.specials += Instance("IBUFDS",
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i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
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o_O=rtio_external_clk)
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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ext_clkout_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.01,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=~self._clock_sel.storage,
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# VCO @ 1GHz when using 125MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self._pll_reset.storage,
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o_CLKFBOUT=rtio_clk,
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p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk,
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p_CLKOUT1_DIVIDE=5, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=ext_clkout_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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Instance("BUFG", i_I=ext_clkout_clk, o_O=self.cd_ext_clkout.clk),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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MultiReg(pll_locked, self._pll_locked.status)
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]
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# The default user SMA voltage on KC705 is 2.5V, and the Migen platform
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# follows this default. But since the SMAs are on the same bank as the DDS,
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# which is set to 3.3V by reprogramming the KC705 power ICs, we need to
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# redefine them here.
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_sma33_io = [
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("user_sma_gpio_p_33", 0, Pins("Y23"), IOStandard("LVCMOS33")),
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("user_sma_gpio_n_33", 0, Pins("Y24"), IOStandard("LVCMOS33")),
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]
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_ams101_dac = [
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("ams101_dac", 0,
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Subsignal("ldac", Pins("XADC:GPIO0")),
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Subsignal("clk", Pins("XADC:GPIO1")),
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Subsignal("mosi", Pins("XADC:GPIO2")),
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Subsignal("cs_n", Pins("XADC:GPIO3")),
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IOStandard("LVTTL")
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)
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]
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_sdcard_spi_33 = [
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("sdcard_spi_33", 0,
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Subsignal("miso", Pins("AC20"), Misc("PULLUP=TRUE")),
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Subsignal("clk", Pins("AB23")),
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Subsignal("mosi", Pins("AB22")),
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Subsignal("cs_n", Pins("AC21")),
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IOStandard("LVCMOS33")
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)
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]
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_zotino = [
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("fmcdio_dirctl", 0,
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Subsignal("clk", Pins("HPC:LA32_N")),
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Subsignal("ser", Pins("HPC:LA33_P")),
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Subsignal("latch", Pins("HPC:LA32_P")),
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IOStandard("LVCMOS25")
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),
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("zotino_spi_p", 0,
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Subsignal("clk", Pins("HPC:LA08_P")),
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Subsignal("mosi", Pins("HPC:LA09_P")),
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Subsignal("miso", Pins("HPC:LA10_P")),
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Subsignal("cs_n", Pins("HPC:LA11_P")),
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IOStandard("LVDS_25")
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),
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("zotino_spi_n", 0,
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Subsignal("clk", Pins("HPC:LA08_N")),
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Subsignal("mosi", Pins("HPC:LA09_N")),
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Subsignal("miso", Pins("HPC:LA10_N")),
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Subsignal("cs_n", Pins("HPC:LA11_N")),
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IOStandard("LVDS_25")
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),
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("zotino_ldac", 0,
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Subsignal("p", Pins("HPC:LA13_P")),
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Subsignal("n", Pins("HPC:LA13_N")),
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IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
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)
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]
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# FMC DIO 32ch LVDS a v1.2 on HPC to VHDCI-Carrier v1.1
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# uring the upper/right VHDCI connector: LVDS7 and LVDS8
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# using the lower/left VHDCI connector: LVDS3 and LVDS4
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_urukul = [
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("urukul_spi_p", 0,
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Subsignal("clk", Pins("HPC:LA17_CC_P")),
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Subsignal("mosi", Pins("HPC:LA16_P")),
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Subsignal("miso", Pins("HPC:LA24_P")),
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Subsignal("cs_n", Pins("HPC:LA19_P HPC:LA20_P HPC:LA21_P")),
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IOStandard("LVDS_25"),
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),
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("urukul_spi_n", 0,
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Subsignal("clk", Pins("HPC:LA17_CC_N")),
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Subsignal("mosi", Pins("HPC:LA16_N")),
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Subsignal("miso", Pins("HPC:LA24_N")),
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Subsignal("cs_n", Pins("HPC:LA19_N HPC:LA20_N HPC:LA21_N")),
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IOStandard("LVDS_25"),
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),
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("urukul_io_update", 0,
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Subsignal("p", Pins("HPC:LA22_P")),
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Subsignal("n", Pins("HPC:LA22_N")),
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IOStandard("LVDS_25"),
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),
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("urukul_dds_reset", 0,
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Subsignal("p", Pins("HPC:LA23_P")),
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Subsignal("n", Pins("HPC:LA23_N")),
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IOStandard("LVDS_25"),
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),
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("urukul_sync_clk", 0,
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Subsignal("p", Pins("HPC:LA18_CC_P")),
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Subsignal("n", Pins("HPC:LA18_CC_N")),
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IOStandard("LVDS_25"),
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),
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("urukul_sync_in", 0,
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Subsignal("p", Pins("HPC:LA25_P")),
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Subsignal("n", Pins("HPC:LA25_N")),
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IOStandard("LVDS_25"),
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),
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("urukul_io_update_ret", 0,
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Subsignal("p", Pins("HPC:LA26_P")),
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Subsignal("n", Pins("HPC:LA26_N")),
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IOStandard("LVDS_25"),
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),
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("urukul_sw0", 0,
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Subsignal("p", Pins("HPC:LA28_P")),
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Subsignal("n", Pins("HPC:LA28_N")),
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IOStandard("LVDS_25"),
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),
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("urukul_sw1", 0,
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Subsignal("p", Pins("HPC:LA29_P")),
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Subsignal("n", Pins("HPC:LA29_N")),
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IOStandard("LVDS_25"),
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),
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("urukul_sw2", 0,
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Subsignal("p", Pins("HPC:LA30_P")),
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Subsignal("n", Pins("HPC:LA30_N")),
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IOStandard("LVDS_25"),
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),
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("urukul_sw3", 0,
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Subsignal("p", Pins("HPC:LA31_P")),
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Subsignal("n", Pins("HPC:LA31_N")),
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IOStandard("LVDS_25"),
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)
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]
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class _StandaloneBase(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x20000000,
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"rtio_dma": 0x30000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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self.platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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if isinstance(self.platform.toolchain, XilinxISEToolchain):
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self.platform.toolchain.bitgen_opt += " -g compress"
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self.submodules.timer1 = timer.Timer()
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self.csr_devices.append("timer1")
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self.interrupt_devices.append("timer1")
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self.submodules.leds = gpio.GPIOOut(Cat(
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self.platform.request("user_led", 0),
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self.platform.request("user_led", 1)))
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self.csr_devices.append("leds")
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self.platform.add_extension(_sma33_io)
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self.platform.add_extension(_ams101_dac)
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self.platform.add_extension(_sdcard_spi_33)
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self.platform.add_extension(_zotino)
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self.platform.add_extension(_urukul)
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_DDS"] = None
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
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self.csr_devices.append("rtio_crg")
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self.config["HAS_RTIO_CLOCK_SWITCH"] = None
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self.submodules.rtio_core = rtio.Core(rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
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self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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class NIST_CLOCK(_StandaloneBase):
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"""
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NIST clock hardware, with old backplane and 11 DDS channels
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"""
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def __init__(self, **kwargs):
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_StandaloneBase.__init__(self, **kwargs)
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platform = self.platform
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platform.add_extension(nist_clock.fmc_adapter_io)
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rtio_channels = []
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for i in range(16):
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if i % 4 == 3:
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phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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else:
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phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for i in range(2):
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phy = ttl_serdes_7series.InOut_8X(platform.request("pmt", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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phy = ttl_simple.Output(platform.request("user_led", 2))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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ams101_dac = self.platform.request("ams101_dac", 0)
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phy = ttl_simple.Output(ams101_dac.ldac)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = ttl_simple.ClockGen(platform.request("la32_p"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = spi2.SPIMaster(ams101_dac)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ififo_depth=4))
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for i in range(3):
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phy = spi2.SPIMaster(self.platform.request("spi", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ififo_depth=128))
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phy = spi2.SPIMaster(platform.request("sdcard_spi_33"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ififo_depth=4))
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fmcdio_dirctl = self.platform.request("fmcdio_dirctl")
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for s in fmcdio_dirctl.clk, fmcdio_dirctl.ser, fmcdio_dirctl.latch:
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phy = ttl_simple.Output(s)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sdac_phy = spi2.SPIMaster(self.platform.request("zotino_spi_p"),
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self.platform.request("zotino_spi_n"))
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self.submodules += sdac_phy
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rtio_channels.append(rtio.Channel.from_phy(sdac_phy, ififo_depth=4))
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pads = platform.request("zotino_ldac")
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ldac_phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += ldac_phy
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rtio_channels.append(rtio.Channel.from_phy(ldac_phy))
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dac_monitor = ad53xx_monitor.AD53XXMonitor(sdac_phy.rtlink, ldac_phy.rtlink)
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self.submodules += dac_monitor
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sdac_phy.probes.extend(dac_monitor.probes)
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phy = spi2.SPIMaster(self.platform.request("urukul_spi_p"),
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self.platform.request("urukul_spi_n"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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for signal in "io_update dds_reset sw0 sw1 sw2 sw3".split():
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pads = platform.request("urukul_{}".format(signal))
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phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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class NIST_QC2(_StandaloneBase):
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"""
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NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
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and 24 DDS channels. Two backplanes are used.
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"""
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def __init__(self, **kwargs):
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_StandaloneBase.__init__(self, **kwargs)
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platform = self.platform
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platform.add_extension(nist_qc2.fmc_adapter_io)
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rtio_channels = []
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clock_generators = []
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# All TTL channels are In+Out capable
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for i in range(40):
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phy = ttl_serdes_7series.InOut_8X(
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platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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# CLK0, CLK1 are for clock generators, on backplane SMP connectors
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for i in range(2):
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phy = ttl_simple.ClockGen(
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platform.request("clkout", i))
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self.submodules += phy
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clock_generators.append(rtio.Channel.from_phy(phy))
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# user SMA on KC705 board
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phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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phy = ttl_simple.Output(platform.request("user_led", 2))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
# AMS101 DAC on KC705 XADC header - optional
|
|
ams101_dac = self.platform.request("ams101_dac", 0)
|
|
phy = ttl_simple.Output(ams101_dac.ldac)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
# add clock generators after TTLs
|
|
rtio_channels += clock_generators
|
|
|
|
phy = spi2.SPIMaster(ams101_dac)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(
|
|
phy, ififo_depth=4))
|
|
|
|
for i in range(4):
|
|
phy = spi2.SPIMaster(self.platform.request("spi", i))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(
|
|
phy, ififo_depth=128))
|
|
|
|
for backplane_offset in range(2):
|
|
phy = dds.AD9914(
|
|
platform.request("dds", backplane_offset), 12, onehot=True)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
|
|
|
|
self.config["HAS_RTIO_LOG"] = None
|
|
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
|
|
rtio_channels.append(rtio.LogChannel())
|
|
|
|
self.add_rtio(rtio_channels)
|
|
|
|
|
|
_sma_spi = [
|
|
("sma_spi", 0,
|
|
Subsignal("clk", Pins("Y23")), # user_sma_gpio_p
|
|
Subsignal("cs_n", Pins("Y24")), # user_sma_gpio_n
|
|
Subsignal("mosi", Pins("L25")), # user_sma_clk_p
|
|
Subsignal("miso", Pins("K25")), # user_sma_clk_n
|
|
IOStandard("LVCMOS25")),
|
|
]
|
|
|
|
|
|
class SMA_SPI(_StandaloneBase):
|
|
"""
|
|
SPI on 4 SMA for PDQ2 test/demo.
|
|
"""
|
|
def __init__(self, **kwargs):
|
|
_StandaloneBase.__init__(self, **kwargs)
|
|
|
|
platform = self.platform
|
|
self.platform.add_extension(_sma_spi)
|
|
|
|
rtio_channels = []
|
|
|
|
phy = ttl_simple.Output(platform.request("user_led", 2))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
ams101_dac = self.platform.request("ams101_dac", 0)
|
|
phy = ttl_simple.Output(ams101_dac.ldac)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
|
|
phy = spi2.SPIMaster(ams101_dac)
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(
|
|
phy, ififo_depth=4))
|
|
|
|
phy = spi2.SPIMaster(self.platform.request("sma_spi"))
|
|
self.submodules += phy
|
|
rtio_channels.append(rtio.Channel.from_phy(
|
|
phy, ififo_depth=128))
|
|
|
|
self.config["HAS_RTIO_LOG"] = None
|
|
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
|
|
rtio_channels.append(rtio.LogChannel())
|
|
|
|
self.add_rtio(rtio_channels)
|
|
|
|
def add_rtio(self, rtio_channels):
|
|
self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk,
|
|
use_sma=False)
|
|
self.csr_devices.append("rtio_crg")
|
|
self.config["HAS_RTIO_CLOCK_SWITCH"] = None
|
|
self.submodules.rtio_core = rtio.Core(rtio_channels)
|
|
self.csr_devices.append("rtio_core")
|
|
self.submodules.rtio = rtio.KernelInitiator()
|
|
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
|
|
rtio.DMA(self.get_native_sdram_if()))
|
|
self.register_kernel_cpu_csrdevice("rtio")
|
|
self.register_kernel_cpu_csrdevice("rtio_dma")
|
|
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
|
[self.rtio.cri, self.rtio_dma.cri],
|
|
[self.rtio_core.cri])
|
|
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
|
self.csr_devices.append("rtio_moninj")
|
|
|
|
self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
|
|
self.platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk,
|
|
self.rtio_crg.cd_rtio.clk)
|
|
|
|
self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
|
|
self.get_native_sdram_if())
|
|
self.csr_devices.append("rtio_analyzer")
|
|
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(
|
|
description="KC705 gateware and firmware builder")
|
|
builder_args(parser)
|
|
soc_kc705_args(parser)
|
|
parser.set_defaults(output_dir="artiq_kc705")
|
|
parser.add_argument("-V", "--variant", default="nist_clock",
|
|
help="variant: "
|
|
"nist_clock/nist_qc2/sma_spi "
|
|
"(default: %(default)s)")
|
|
args = parser.parse_args()
|
|
|
|
variant = args.variant.lower()
|
|
if variant == "nist_clock":
|
|
cls = NIST_CLOCK
|
|
elif variant == "nist_qc2":
|
|
cls = NIST_QC2
|
|
elif variant == "sma_spi":
|
|
cls = SMA_SPI
|
|
else:
|
|
raise SystemExit("Invalid variant (-V/--variant)")
|
|
|
|
soc = cls(**soc_kc705_argdict(args))
|
|
build_artiq_soc(soc, builder_argdict(args))
|
|
|
|
|
|
if __name__ == "__main__":
|
|
main()
|