forked from M-Labs/artiq
Robert Jordens
4a0eaf0f95
gateware: add jesd204b awg gateware: copy phaser (df3825a) dsp/tools: update satadd mixin phaser: no DDS stubs dsp: accu fix phaser: cleanup/reduce sawg: kernel support and docs sawg: coredevice api fixes sawg: example ddb/experiment phaser: add conda package examples/phaser: typo sawg: adapt tests, fix accu stb sawg: tweak dds parameters sawg: move/adapt/extend tests sawg: test phy, refactor phaser: non-rtio spi phaser: target cli update phaser: ad9154-fmc-ebz pins phaser: reorganize fmc signal naming phaser: add test mode stubs phaser: txen is LVTTL phaser: clk spi xfer test phaser: spi for ad9154 and ad9516 phaser: spi tweaks ad9154: add register map from ad9144.xml ad9516: add register map from ad9517.xml and manual adaptation ad9154_reg: just generate getter/setter macros as well ad9154: reg WIP ad9154: check and fix registers kc705: single ended rtio_external_clk use single ended user_sma_clk_n instead of p/n to free up one clock sma kc705: mirror clk200 at user_sma_clock_p ad9516_regs.h: fix B_COUNTER_MSB phase: wire up clocking differently needs patched misoc kc705: feed rtio_external_clock directly kc705: remove rtio_external_clk for phaser phaser: spi tweaks ad9516: some startup ad9516_reg fixes phaser: setup ad9516 for supposed 500 MHz operation ad9516: use full duplex spi ad9154_reg: add CONFIG_REG_2 ad9154_reg: fixes phaser: write some ad9154 config ad9154_reg: fixes ad9154: more init, and human readable setup ad9154/ad9516: merge spi support ad9154: status readout Revert "kc705: remove rtio_external_clk for phaser" This reverts commit d500288bb44f2bf2eeb0c2f237aa207b0a8b1366. Revert "kc705: feed rtio_external_clock directly" This reverts commit 8dc7825519e3e75b7d3d29c9abf10fc6e3a8b4c5. Revert "phase: wire up clocking differently" This reverts commit ad9cc450ffa35abb54b0842d56f6cf6c53c6fbcc. Revert "kc705: mirror clk200 at user_sma_clock_p" This reverts commit 7f0dffdcdd28e648af84725682f82ec6e5642eba. Revert "kc705: single ended rtio_external_clk" This reverts commit a9426d983fbf5c1cb768da8f1da26d9b7335e9cf. ad9516: 2000 MHz clock phaser: test clock dist phaser: test freqs ad9154: iostandards phaser: drop clock monitor phaser: no separate i2c phaser: drive rtio from refclk, wire up sysref phaser: ttl channel for sync ad9154: 4x interp, status, tweaks phaser: sync/sysref 33V banks phaser: sync/sysref LVDS_25 inputs are VCCO tolerant phaser: user input-only ttls phaser: rtio fully from refclk ad9154: reg name usage fix ad9154: check register modifications Revert "ad9154: check register modifications" This reverts commit 45121d90edf89f7bd8703503f9f317ad050f9564. ad9154: fix status code ad9154: addrinc, recal serdes pll phaser: coredevice, example tweaks sawg: missing import sawg: type fixes ad9514: move setup functions ad9154: msb first also decreasing addr phaser: use sys4x for rtio internal ref phaser: move init code to main phaser: naming cleanup phaser: cleanup pins phaser: move spi to kernel cpu phaser: kernel support for ad9154 spi ad9154: add r/w methods ad9154: need return annotations ad9154: r/w methods are kernels ad9154_reg: portable helpers phaser: cleanup startup kernel ad9154: status test ad9154: prbs test ad9154: move setup, document phaser: more documentation
113 lines
3.2 KiB
Python
113 lines
3.2 KiB
Python
from migen import *
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from misoc.interconnect.stream import Endpoint
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class Accu(Module):
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def __init__(self, width, meta=[]):
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self.i = Endpoint([("p", width), ("f", width), ("clr", 1)])
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self.o = Endpoint([("z", width)])
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self.latency = 1
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###
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f = Signal.like(self.i.f)
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p = Signal.like(self.i.p)
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self.comb += self.i.ack.eq(~self.o.stb | self.o.ack)
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self.sync += [
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If(self.o.ack,
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self.o.stb.eq(0),
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),
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If(self.i.ack,
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self.o.stb.eq(1),
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If(self.i.stb,
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self.o.z.eq(self.i.p + Mux(self.i.clr, 0, self.o.z + p)),
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f.eq(self.i.f),
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p.eq(self.i.f - self.i.p),
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).Else(
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self.o.z.eq(self.o.z + f),
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)
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)
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]
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class MCM(Module):
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def __init__(self, width, constants):
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n = len(constants)
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self.i = i = Signal(width)
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self.o = o = [Signal.like(self.i) for i in range(n)]
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###
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# TODO: improve MCM
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assert range(n) == constants
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assert n <= 9
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if n > 0:
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self.comb += o[0].eq(0)
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if n > 1:
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self.comb += o[1].eq(i)
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if n > 2:
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self.comb += o[2].eq(i << 1)
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if n > 3:
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self.comb += o[3].eq(i + (i << 1))
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if n > 4:
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self.comb += o[4].eq(i << 2)
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if n > 5:
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self.comb += o[5].eq(i + (i << 2))
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if n > 6:
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self.comb += o[6].eq(o[3] << 1)
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if n > 7:
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self.comb += o[7].eq((i << 3) - i)
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if n > 8:
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self.comb += o[8].eq(i << 3)
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class PhasedAccu(Module):
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def __init__(self, width, parallelism=8):
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self.i = Endpoint([("p", width), ("f", width), ("clr", 1)])
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self.o = Endpoint([("z{}".format(i), width) for i in
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range(parallelism)])
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self.parallelism = parallelism
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self.latency = 2
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###
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a = MCM(width, range(parallelism + 1))
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self.submodules += a
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z = [Signal(width) for i in range(parallelism)]
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o = self.o.payload.flatten()
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load = Signal()
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clr = Signal()
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p = Signal.like(self.i.p)
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f = Signal.like(self.i.f)
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fp = Signal.like(self.i.f)
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self.comb += [
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self.i.ack.eq(self.o.ack),
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a.i.eq(self.i.f),
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]
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self.sync += [
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If(self.o.ack,
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self.o.stb.eq(0),
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),
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If(~self.o.stb | self.o.ack,
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self.o.stb.eq(1),
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If(load,
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load.eq(0),
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[oi.eq(Mux(clr, 0, o[0] + fp) + zi)
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for oi, zi in zip(o, z)],
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fp.eq(f),
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).Else(
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[oi.eq(oi + fp) for oi in o],
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),
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),
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If(self.i.stb & self.i.ack,
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[zi.eq(self.i.p - Mux(self.i.clr, 0, p) + aoi)
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for zi, aoi in zip(z, a.o)],
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clr.eq(self.i.clr),
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p.eq(self.i.p),
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f.eq(a.o[parallelism]),
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load.eq(1),
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),
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]
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