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6751 Commits

Author SHA1 Message Date
Drew 66861e6708 test_pc_rpc: fix equality bug (#1188) (#1239) 
Fixes bug from 5108ed8. Truth value of multi-element numpy array is
not defined. Completes #1186 and fixes/amends #1188.

Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
 2019-01-11 10:15:44 +08:00
Robert Jördens 101671fbbf core_analyzer: support uniform VCD time intervals 
close #1236

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-10 19:35:09 +01:00
Drew 58e872e7b5 doc: document artiq_coreanalyzer usage. (#1233) 2019-01-10 13:01:36 +08:00
Drew 99a0f61b35 artiq_client: remove custom input validation for built-in argparse (#1185) 2019-01-10 12:58:11 +08:00
Drew 721c6f3bcc pc_rpc: fix handling of type annotations 2019-01-10 12:13:22 +08:00
Robert Jördens 088530604e test_ad9910: relax tests 
* tune_sync_delay: the opposite IO_UPDATE to SYNC_CLK alignment may not be perfectly
mis-aligned
* set_mu_speed: seems to be slower on the buildbot

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-09 17:27:42 +00:00
Robert Jördens 19748fe495 ad9910: fix RTIO fine timestamp nudging 
Previously the TSC was truncated to an even coarse RTIO periods before doing
the setting SPI xfer. Afterwards the the IO update pulse would introduce
at least one but less than two RTIO cycles. Ultimately the RTIO TSC was
truncated again to even. If the SPI xfer takes an odd number of RTIO
periods, then a subsequent xfer would collide.

close #1229

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-09 17:22:57 +00:00
Robert Jördens b25ab1fc88 ad9910: add more slack in tune_sync_delay 
close #1235

Signed-off-by: Robert Jördens <rj@quartiq.de>
 2019-01-09 16:07:31 +00:00
Sebastien Bourdeauducq f8a94725e9 manual: add precision about sequence errors 2019-01-09 18:58:22 +08:00
Sebastien Bourdeauducq 9b213b17af sayma_amc: forward RTM UART in Master variant as well 2019-01-09 18:57:57 +08:00
Sebastien Bourdeauducq c7b18952b8 sayma_amc: work around Ultrascale LVDS Toutbuf_delay_td_pad 2019-01-09 13:47:08 +08:00
Sebastien Bourdeauducq 62599c5f91 firmware: use consistent terminology 2019-01-09 13:46:18 +08:00
Drew b3b0b6f0a5 artiq_influxdb: clarify argparse groups (#1212) 
Make names of argparse group variables relate to what they're doing.
Meets Flake8.

Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
 2019-01-09 11:40:55 +08:00
David Nadlinger 101ed5d534 examples: Fix DRTIO destination indices (#1231) 
Using the default routing table, links numbers and destinations
are offset by 1, as destination 0 is local RTIO.
 2019-01-09 11:40:15 +08:00
Drew 40370c4d45 Docs: fix build warnings (#1234) 
* ad9910: finish CONT_RECIRCULATE -> CONT_RAMPUP

Found while building docs. Forgot to refactor strings.

Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>

* spi2: reformat update_xfer_duration_mu docstring

update_xfer_duration_mu docstring threw warning while building docs,
didn't use consistent indent in warning.

Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
 2019-01-09 11:39:23 +08:00
David Nadlinger 4fb434674d coredevice: Fix ad9910 __all__ exports 2019-01-08 18:55:26 +00:00
Sebastien Bourdeauducq 0d3e7ba805 nix: add zlib in artiq-dev 
Needed by the Vivado installer.
 2019-01-08 20:47:09 +08:00
Sebastien Bourdeauducq 887cb110a7 firmware: fix default DRTIO routing table 2019-01-08 20:46:53 +08:00
David Nadlinger cadde970e1 urukul: Expand CPLD sync_sel explanation [nfc] 2019-01-08 02:37:58 +00:00
David Nadlinger 7bcdeb825b ad9910: Add inverse FTW/ASF conversions 2019-01-08 02:18:14 +00:00
David Nadlinger 4d793d7149 ad9910: Truncate phase word to 16 bits 
This avoids overflowing into the asf portion of the register.
 2019-01-08 02:18:14 +00:00
Sebastien Bourdeauducq 332bd6090f satman: wait for CPLL/QPLL lock after setting drtio_transceiver::stable_clkin 2019-01-07 17:09:19 +08:00
Sebastien Bourdeauducq 3217488824 add Sayma RTM DRTIO target 2019-01-07 00:13:47 +08:00
Sebastien Bourdeauducq b5501aaf00 firmware: program I2C switch on Sayma RTM 2019-01-06 14:54:52 +08:00
Sebastien Bourdeauducq 66b3132c28 sayma_amc: fix RTIO TSC instantiation 2019-01-06 14:54:32 +08:00
Sebastien Bourdeauducq 6e43c41103 firmware: support building without SDRAM 2019-01-05 23:41:30 +08:00
Sebastien Bourdeauducq cf9447ab77 rtio/cri: remove unneeded CSR management 2019-01-05 23:40:45 +08:00
Sebastien Bourdeauducq 2c3510497b firmware: fix not(has_spiflash) build 2019-01-05 23:40:03 +08:00
Sebastien Bourdeauducq d6fea22174 manual: update firmware/gateware build/flashing instructions. Closes #1223 2019-01-05 12:38:54 +08:00
Sebastien Bourdeauducq 2100a8b1f1 sayma_amc: more fighting with vivado timing analyzer 2019-01-05 12:25:30 +08:00
Drew 94cdad6c1d artiq_flash: change docs from old `-m` arg to `-V` (#1224) (#1227) 
`-m` argument is deprecated. Changed to newer `-V` argument
Closes #1224

Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
 2019-01-05 10:22:12 +08:00
Drew Risinger b58d59a9e7 pyon: fix grammar in module docstring. 
Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
 2019-01-04 19:31:08 +00:00
Drew 3e5cea5d89 Docs: instructions to check if in plugdev group 2019-01-04 19:30:13 +00:00
Sebastien Bourdeauducq a93fdb8c9d drtio: disable all destinations in gateware at startup 
Otherwise, kernels fail to get a RTIODestinationUnreachable exception when attempting
to reach a DRTIO destination that has never been up.
 2019-01-04 23:42:12 +08:00
Sebastien Bourdeauducq 62d7c89c48 sayma_amc: use high-resolution TTL on SMAs (#792) 2019-01-03 20:50:38 +08:00
Sebastien Bourdeauducq 0972d61e81 ttl_serdes_ultrascale: use GTH clock domains 2019-01-03 20:50:04 +08:00
Sebastien Bourdeauducq f007895fad drtio/gth_ultrascale: fix rtiox clock domain 2019-01-03 20:49:38 +08:00
Sebastien Bourdeauducq 10ebf63c47 jesd204_tools: get the Vivado timing analyzer to behave 2019-01-03 20:22:35 +08:00
Sebastien Bourdeauducq d6a3172a3e update copyright year 2019-01-03 20:21:34 +08:00
Sebastien Bourdeauducq 4af8fd6a0d ttl_serdes_ultrascale: fix Input 2019-01-03 20:14:54 +08:00
Sebastien Bourdeauducq 175f8b8ccc drtio/gth_ultrascale: generate multiplied RTIO clock from BUFG_GT (#792) 2019-01-03 20:14:18 +08:00
Sebastien Bourdeauducq 77126ce5b3 kasli: use hwrev 1.1 by default for DRTIO examples 2019-01-02 23:04:20 +08:00
Sebastien Bourdeauducq ab9ca0ee0a kasli: use 150MHz for DRTIO by default (Sayma compatibility) 2019-01-02 23:03:57 +08:00
Sebastien Bourdeauducq cc58318500 siphaser: autocalibrate skew using RX synchronizer 
* removes the hardcoded, (poorly) manually determined skew value
* does not need si5324_clkout_fabric anymore (broken on Sayma RTM due to wrong IO voltage)
 2019-01-02 22:29:27 +08:00
Sebastien Bourdeauducq f5cda3689e sayma_amc: enable DRTIO on master SATA connector for MasterDAC variant 2019-01-02 16:46:16 +08:00
Sebastien Bourdeauducq e85df13127 nix: update docs 2019-01-02 16:34:29 +08:00
Sebastien Bourdeauducq ec52a1003d nix: add jesd204b 2019-01-02 16:34:11 +08:00
Sebastien Bourdeauducq d42d607547 nix: add microscope 2019-01-02 16:13:08 +08:00
Sebastien Bourdeauducq 7a6bdcb041 nix: fix m-labs URLs 2019-01-02 16:04:25 +08:00
Sebastien Bourdeauducq 48793b7ecf nix: reorganize .nix files 2019-01-01 23:39:38 +08:00