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8,305 Commits 14 Branches 35 Tags 23 MiB
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8305 Commits

Author SHA1 Message Date
occheung 7542105f0f board_misoc: remove pcr 
VexRiscv seems to not support additional hardware performance counter, at least I have not seen any documentation on how to use it.
 2021-09-10 13:25:12 +08:00
occheung 01ca114c66 runtime: remove irq dependency 2021-09-10 13:25:12 +08:00
occheung 36171f2c61 runtime: remove inaccurate sp on panic 2021-09-10 13:25:12 +08:00
occheung 01e357e5d3 ksupport.ld: reduce load section alignment 2021-09-10 13:25:12 +08:00
occheung f77b607b56 compiler: generate symbols 2021-09-10 13:25:12 +08:00
occheung 1293e0750e ld, makefiles: use ld.lld 2021-09-10 13:25:12 +08:00
occheung fc42d053d9 kernel: use vexriscv 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 9adab6c817 flake: add devshell 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 8c468d0346 flake: switch to nightly rust with mozilla overlay 2021-09-10 13:25:12 +08:00
occheung 1b516b16e2 targets: default to vexriscv cpu 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq be5ae5c5b4 flake: configure binary cache 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq d13efd6587 add Nix flake 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq e8fe8409b2 libartiq_support: compatibility with recent stable rustc 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq cabe5ace8e compiler: remove DebugInfoEmitter for now 
Causes problems with LLVM 9 and not needed at first.
 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 6629a49e86 compiler: use LLVM binutils/linker for Arm as well 
Previously we kept GNU Binutils because they are less of a pain to support
on Windoze - the source of so many problems - but with RISC-V we need to
update LLVM anyway.
 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 43d120359d compiler: switch to upstream llvmlite and RISC-V target 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 5656e52581 remove profiler 2021-09-10 13:25:12 +08:00
occheung 1b8b4baf6a ksupport: fix panic, libc, unwind 2021-09-10 13:25:12 +08:00
occheung 905330b0f1 ksupport: handle riscv exceptions 2021-09-10 13:25:12 +08:00
occheung 50a62b3d42 liballoc: change align to 16 bytes 2021-09-10 13:25:12 +08:00
occheung 7f0bc9f7f0 runtime/makefile: specify emulation, flip endianness 2021-09-10 13:25:12 +08:00
occheung c42adfe6fd runtime.ld: merge .sbss & .bss 2021-09-10 13:25:12 +08:00
occheung f56152e72f rust: fix dependencies 2021-09-10 13:25:12 +08:00
occheung c800b6c8d3 runtime: update rust alloc, managed 2021-09-10 13:25:09 +08:00
occheung e99061b013 runtime: add riscv 2021-09-10 13:23:22 +08:00
occheung ecedec577c runtime: impl riscv exception handling 2021-09-10 13:23:15 +08:00
occheung 252594a606 runtime: impl riscv panic handler 2021-09-10 13:20:31 +08:00
occheung 31bf17563c personality: update from rust/panic_unwind 2021-09-10 13:20:31 +08:00
occheung bfddd8a30f libdyld: add riscv support 2021-09-10 13:20:31 +08:00
occheung ad3037d0f6 libc: add minimal C types 2021-09-10 13:20:31 +08:00
occheung daaf6c3401 libunwind: add rust interface 2021-09-10 13:20:31 +08:00
occheung 6d9cebfd42 satman: handle .sbss generation 2021-09-10 13:20:31 +08:00
occheung 96438c9da7 satman: make fbi big-endian 2021-09-10 13:20:31 +08:00
occheung 6535b2f089 satman: fix feature 2021-09-10 13:20:31 +08:00
occheung 45adaa1d98 satman: add riscv exception handling 2021-09-10 13:20:31 +08:00
occheung 869a282410 satman: use riscv 2021-09-10 13:20:31 +08:00
occheung ebb9f298b5 proto_artiq: update alloc type path 2021-09-10 13:20:31 +08:00
occheung 97a0132f15 libio: update alloc type path 2021-09-10 13:20:31 +08:00
occheung 37ea863004 libio: pin failure version 2021-09-10 13:20:31 +08:00
occheung 3ff74e0693 bootloader: handle .sbss generation in .ld 
Signed-off-by: occheung <dc@m-labs.hk>
 2021-09-10 13:20:31 +08:00
occheung 448fe0e8cf bootloader: fix panic 
Signed-off-by: occheung <dc@m-labs.hk>
 2021-09-10 13:20:31 +08:00
occheung 8294d7fea5 bootloader: swap endianness 
Signed-off-by: occheung <dc@m-labs.hk>
 2021-09-10 13:20:31 +08:00
occheung 13032272fd bootloader: add rv32 exception handler 
Signed-off-by: occheung <dc@m-labs.hk>
 2021-09-10 13:20:31 +08:00
occheung 46102ee737 board_misoc: build vectors.S with rv64 target in misoc 
Signed-off-by: occheung <dc@m-labs.hk>
 2021-09-10 13:20:31 +08:00
occheung b87ea79d51 rv32: rm irq & vexriscv-rust 
Signed-off-by: occheung <dc@m-labs.hk>
 2021-09-10 13:20:31 +08:00
occheung 9aee42f0f2 rv32/boot: remove hotswap 
Signed-off-by: occheung <dc@m-labs.hk>
 2021-09-10 13:20:31 +08:00
occheung 82b4052cd6 libboard_misoc: vexriscv integration 
Signed-off-by: occheung <dc@m-labs.hk>
 2021-09-10 13:20:31 +08:00
Leon Riesebos 2cf144a60c ddb_template: edge counter keys correspond with according ttl keys 
previously ttl_counter_0 and ttl_0 could be on completely different physical ttl output channels
with this change, ttl_0_counter (note the changed key format) is always on the same channel as ttl_0

Signed-off-by: Leon Riesebos <leon.riesebos@duke.edu>
 2021-09-06 09:06:04 +08:00
Robert Jördens e7a46ec767
Merge pull request #1749 from airwoodix/phaser-frame-alignment-utils 
Phaser: add helpers to align updates with RTIO timeline
 2021-09-03 14:00:17 +02:00
Etienne Wodey 4d7bd3ee32 phaser: fail init() if frame timestamp measurement times out 
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
 2021-09-03 12:01:26 +02:00