423929a125
test: relax min transfer rates from 2MB/s to 1.9MB/s
2018-07-09 18:00:24 +08:00
9153c4d8a3
use tokenize.open() to open Python source files
...
Fixes encoding issues especially with device databases modified in obscure editors.
2018-07-07 17:04:56 +08:00
4420046502
kasli_tester: support mixed AD9910/AD9912 systems
2018-07-06 15:43:38 +08:00
ac3f360c26
kasli_tester: fix AD9912 support
2018-07-06 15:43:25 +08:00
509562ddbf
kasli: add WIPM target
2018-07-06 15:41:28 +08:00
4eb26c0050
hmc7043: enable group 5
2018-07-03 14:16:31 +02:00
540bdae99c
grabber: enable DIFF_TERM on inputs
2018-07-01 09:28:51 +08:00
0483b8d14c
sayma_drtio: ditto
2018-06-28 17:03:32 +08:00
04d6ff45c8
kasli_sawgmaster: reset SAWGs
...
Most importantly this resets the phase accumulators.
2018-06-28 17:01:48 +08:00
729ce58f98
sayma: use GTP_CLK1 to clock DRTIO satellite transceiver
...
This is required to get constant skew between the DRTIO transceiver clock
(which then generates the RTIO clock) and the siphaser reference clock.
Both the Si5324 and the RTM clock tree have non-deterministic in-to-out skew
at 150MHz due to dividers.
2018-06-28 11:23:40 +08:00
a65721d649
sayma: put RTM clock tree into the siphaser loop
...
* Fixes one bug where siphaser was one Si5324 output and the rest of the
system was clocked by the other. With the Si5324 settings we have, skew
between the outputs is not controlled.
* Puts the coaxial cable between AMC and RTM into the siphaser loop.
2018-06-27 21:46:55 +08:00
d49716dfac
satman: tune Sayma SYSREF phases
2018-06-27 18:09:35 +08:00
46c044099c
hmc7043,satman: verify alignment of SYSREF slips
2018-06-27 17:36:13 +08:00
7dfd70c502
hmc7043: make margin_{minus,plus} consistent with ad9154
2018-06-27 17:35:26 +08:00
4bbdd43bdf
hmc7043: do not freeze if SYSREF slip fails
2018-06-27 17:32:56 +08:00
a8a2ad68d3
runtime: tune Sayma SYSREF phases
2018-06-27 17:31:29 +08:00
811882943b
artiq_flash: RTM gateware is not required for master variant
2018-06-25 18:28:55 +08:00
c750de2955
sayma: add many-port pure DRTIO master
2018-06-25 18:21:22 +08:00
84b3d9ecc6
bootloader: also check firmware CRC in SDRAM ( #1065 )
2018-06-23 11:28:12 +08:00
68530fde07
sayma: generate 100MHz from Si5324 on standalone and master targets
...
* Allow switching between DRTIO satellite and standalone without
touching the hardware.
* Allow operating standalone and master without an additional RF
signal generator.
2018-06-23 10:44:38 +08:00
whitequark
b6dd9c8bb0
runtime: support builds without RTIO DMA.
...
Fixes #1079 .
2018-06-23 00:56:21 +00:00
whitequark
12fde6d34b
artiq_coremgmt: fix typo.
...
Fixes #1056 .
2018-06-23 00:36:59 +00:00
51a5d8dff9
examples: add Kasli SAWG master
2018-06-22 18:57:49 +08:00
f87da95e57
jesd204: use jesd clock domain for sysref sampler
...
RTIO domain is still in reset during calibration.
2018-06-22 17:13:01 +08:00
76fc63bbf7
jesd204: use separate controls for reset and input buffer disable
2018-06-22 11:38:18 +08:00
d9955fee76
jesd204: make sure IOB FF is used to sample SYSREF at FPGA
2018-06-22 11:00:56 +08:00
60b22217ce
sayma: set DRTIO master HMC830_REF to 100MHz
2018-06-22 10:10:09 +08:00
e6d1726754
sayma: add RTIO log to DRTIO master
2018-06-22 00:05:22 +08:00
83428961ad
sayma: add SAWG and JESD to DRTIO master
2018-06-22 00:04:22 +08:00
c1db02a351
drtio/gth_ultrascale: disable IBUFDS_GTE3 until stable_clkin
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Precaution against HMC7043 noise issues.
2018-06-21 22:56:07 +08:00
8b3c12e6eb
sayma: clock DRTIO master transceiver from HMC7043
2018-06-21 22:34:44 +08:00
de7d64d482
sayma: clock JESD204 from GTP CLK2
...
This frees up GTP CLK1, which is routable to the SFP quads, for DRTIO.
2018-06-21 22:33:53 +08:00
b28ff587c5
sayma: add sysref sampler to DRTIO master
2018-06-21 22:28:34 +08:00
07bcdfd91e
hmc7043: stricter check of FPGA SYSREF margin
2018-06-21 22:26:49 +08:00
e29536351d
drtio: resync SYSREF when TSC is loaded
2018-06-21 17:00:32 +08:00
5a2a857a2f
firmware: clean up SYSREF phase management
2018-06-21 16:23:41 +08:00
05e908a0fd
hmc7043: align SYSREF with RTIO
2018-06-21 15:54:42 +08:00
9741654cad
hmc7043: style
2018-06-21 15:54:42 +08:00
45e8263208
hmc7043: do not configure phases during initial init
...
They are determined later on.
2018-06-21 15:54:42 +08:00
whitequark
7cc3da4faf
firmware: do not lose the ".dirty" suffix in build versions.
...
Fixes #1074 .
2018-06-21 05:18:51 +00:00
whitequark
095ee28fd9
runtime: fix size values for bytes and bytearray RPCs.
...
Fixes #1076 .
2018-06-21 00:51:56 +00:00
whitequark
9260cdb2e8
compiler: support conversion of list to bytearray and bytes.
...
Fixes #1077 .
2018-06-21 00:40:45 +00:00
5a91f820fd
examples: change Sayma sines frequency to 9MHz
...
Well within Red Pitaya bandwidth.
2018-06-20 22:40:07 +08:00
9288301543
examples: add DRTIO sines
2018-06-20 22:39:40 +08:00
28fb0fd754
sayma: add SYSREF sampler gateware
2018-06-20 17:48:35 +08:00
814d0583db
hmc7043: improve smoothness of sysref phase control
2018-06-20 17:40:48 +08:00
9142a5ab8a
rtio: expose coarse timestamp in RTIO and DRTIO satellite cores
2018-06-20 17:39:54 +08:00
5272c11704
typo
2018-06-20 17:05:20 +08:00
0c32d07e8b
ad9154: new sysref scan
...
Print margins around the pre-defined fixed phase.
Also report error if margins are too small.
The fixed phase is also changed by this commit (the value 88 is
from before the new HMC7043 initialization code, and is probably wrong).
2018-06-20 00:15:58 +08:00
4803ca3799
examples/sayma_drtio: add SAWG channels
2018-06-19 23:50:26 +08:00
3d0e92aefd
hmc7043: check that chip is disabled at startup
2018-06-19 23:49:17 +08:00
740e6863c3
hmc7043: add delay after releasing hardware reset
2018-06-19 23:48:48 +08:00
75b6cea52f
sayma: add SAWG to DRTIO satellite
2018-06-19 19:12:10 +08:00
eb3259b847
firmware: reduce number of DAC initialization attempts
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Faster startup when one DAC is broken.
2018-06-19 19:10:23 +08:00
1d594d0c97
firmware: make DAC initialization failures non-fatal
...
This allows using RTMs with one broken DAC for development.
2018-06-19 19:09:38 +08:00
158b5e3083
satman: program Allaki
2018-06-19 18:09:05 +08:00
574892a4e5
firmware/serwb: cleanup and improve messaging
2018-06-19 15:11:03 +08:00
c862471165
typo
2018-06-19 14:35:24 +08:00
433273dd95
sayma: support RTM FPGA, HMC830 and HMC7043 in DRTIO master and satellite
2018-06-19 14:33:48 +08:00
476cfa0f53
si5324: improve lock messaging
2018-06-19 14:29:57 +08:00
6403a0d5d1
sayma_amc: update without-sawg description
2018-06-19 13:52:05 +08:00
d29b3dd588
hmc830: compile-time configurable reference frequency
2018-06-19 13:47:32 +08:00
6f3ed81626
targets/sayma_rtm: fix description
2018-06-18 17:46:53 +08:00
21a48711ec
i2c: refactor common operations
2018-06-18 09:34:09 +00:00
0e640a6d6f
hmc7043: fix SYSREF to meet s/h at FPGA ( #794 )
2018-06-18 17:04:12 +08:00
6272052d15
ad9154: don't drive the bsm with txen pins
2018-06-18 10:04:42 +02:00
32484a62de
sayma_amc: remove unused imports
2018-06-17 13:09:44 +02:00
4f0c918dd3
slave_fpga: improve messaging
2018-06-17 00:27:27 +08:00
53ab255c00
sayma_amc: enable slave fpga loading ( #813 )
2018-06-16 12:47:26 +02:00
f9910ab242
i2c: support selecting multiple or no channels
...
closes #1054
2018-06-15 19:36:37 +02:00
40baa8ecba
hmc7043: disable ch 10 and 11 group
2018-06-15 15:34:31 +00:00
edfae3c4ba
hmc7043: make fpga fabric clocks lvds
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2 V common and 1.9 Vpp swing
is brutal to the banks (HP 1.8V AMC and RT 1.8V RTM)
2018-06-15 14:24:33 +00:00
f385add8b1
slave_fpga: disable cclk and din drive when done
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to guard against accidental contention (old rtm gateware
but #813 rework done)
2018-06-13 16:26:48 +00:00
1029ac870b
sayma_rtm: don't drive txen pins
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pins disabled by config
necessary for using that pin as DIN (#813 )
2018-06-13 16:11:30 +00:00
68d16fc292
serwb: support single-ended signals
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Low-speed PHY only.
2018-06-13 21:28:21 +08:00
a9a25f2605
sayma_rtm: drive ref_lo_clk_sel, and set clk muxes early
2018-06-12 20:00:12 +02:00
aff7fa008f
Revert "artiq_flash/sayma: check for DONE after load"
...
This reverts commit 2de5b0cf25
2018-06-12 19:14:43 +02:00
2de5b0cf25
artiq_flash/sayma: check for DONE after load
2018-06-13 00:47:43 +08:00
Thomas Harty
b90a8fcc82
Merge branch 'master' of https://github.com/m-labs/artiq
2018-06-12 14:55:22 +01:00
ion
28ecf81c6c
Sayma: HMC7043 init and detect no longer need results.
2018-06-12 13:10:26 +01:00
ion
c8935f7adf
Sayma: bypass dividers where possible to minimize noise (nb this changes the output skew).
2018-06-12 12:56:04 +01:00
hartytp
7a0140ecb2
Sayma HMC830: update interface and register writes. ( #1068 )
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* Break the HMC830 init into separate functions for general purpose (but, integer-N) init, setting dividers and checking lock
* Use 1.6mA ICP (which the loop filter was optimized for)
* Go through the data sheet carefully and set all registers to the correct value (e.g. ensure that all settings are correctly optimized for integer-N usage)
* Change divider values (now using 100MHz PFD, which should give lower noise in theory)
2018-06-12 12:37:17 +01:00
a9d97101fc
slave_fpga: add another check
2018-06-12 10:24:04 +02:00
a143e238a8
savel_fpga: get rid of unneeded config
2018-06-12 10:24:04 +02:00
4912f53ab4
slave_fpga: board_misoc
2018-06-12 10:24:04 +02:00
hartytp
cb6e44b23a
Sayma: disable unused HMC7043 outputs.
2018-06-12 16:18:20 +08:00
0b086225a9
sawg: don't use Cat() for signed signals
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c.f. #1039 #1040 #1022 #1058 #1044
2018-06-09 07:33:47 +00:00
5b73dd8604
sawg: accurate unittest rtio freq
2018-06-08 17:22:13 +02:00
735e4e8561
pcu: spelling
2018-06-08 14:39:22 +00:00
e5f6750171
sawg: cleanup double assign
2018-06-08 14:31:55 +00:00
Florent Kermarrec
53e9e475d0
serwb: transmit zeroes when nothing to transmit (for prbs), improve rx idle detection
2018-06-08 16:10:31 +02:00
Florent Kermarrec
7296a76f18
serwb: move common datapath code to datapath.py, simplify flow control
2018-06-08 12:37:08 +02:00
Florent Kermarrec
89797d08ed
serwb: revert to 125MHz linerate (until we understand why 1gbps version breaks between builds)
2018-06-07 15:13:56 +02:00
b4c2b148d1
sawg: don't use Mux for signed signals
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migen#75
2018-06-06 15:51:14 +00:00
Florent Kermarrec
009db5eda9
serwb: revert 1gbps linerate
2018-06-06 16:20:20 +02:00
cae92f9b44
kasli: add Tsinghua variant
2018-06-06 19:03:45 +08:00
38971d130a
comm_analyzer: fix data without any spi reads
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closes #1050
2018-06-06 12:21:42 +02:00
e21b7965b9
sayma_amc: change test patterns for 'without-sawg'
2018-06-06 08:02:52 +00:00
whitequark
38dac16041
compiler: don't crash when quoting builtin functions.
...
Fixes #1051 .
2018-06-05 23:27:23 +00:00
af88c4c93e
clean up hmc7043 reset
2018-06-05 20:41:48 +08:00
