occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity
7,937 Commits 14 Branches 35 Tags 23 MiB
Commit Graph

7937 Commits

Author SHA1 Message Date
pca006132 ba34700798 coredevice: report nested exceptions 2022-01-26 07:16:54 +08:00
pca006132 6ec003c1c9 compiler: fixed dead code eliminator 
Instead of removing basic blocks with no predecessor, we will now mark
and remove all blocks that are unreachable from the entry block. This
can handle loops that are dead code. This is needed as we will now
generate more complicated code for exception handling which the old dead
code eliminator failed to handle.
 2022-01-26 07:16:54 +08:00
pca006132 da4ff44377 compiler: fixed try codegen and allocate exceptions 
Exceptions are now allocated in the runtime when we raise the exception,
and destroyed when we exit the catch block. Nested exception and try
block is now supported, and should behave the same as in CPython.
Exceptions raised in except blocks will now unwind through finally
blocks, matching the behavior in CPython. Reraise will now preserve
backtrace.

Phi block LLVM IR generation is modified to handle landingpads, which
one ARTIQ IR will map to multiple LLVM IR.
 2022-01-26 07:16:54 +08:00
pca006132 4644e105b1 compiler: modified exception representation 
Exception name is replaced by exception ID, which requires no
allocation. Other strings in the exception can now be 'host-only'
strings, which is represented by a CSlice with len = usize::MAX and
ptr = key, to avoid the need for allocation when raising exceptions
through RPC.
 2022-01-26 07:16:54 +08:00
hartytp 715bff3ebf
Revert "Merge pull request #1544 from airwoodix/dataset-compression" (#1838) 
* Revert "Merge pull request #1544 from airwoodix/dataset-compression"

This reverts commit 311a818a49, reversing
changes made to 7ffe4dc2e3.

* fix accidental revert of f42bea06a8
 2022-01-25 10:02:15 +08:00
Sebastien Bourdeauducq f58aa3bdf6 flake: update qasync 2022-01-19 20:44:50 +08:00
Sebastien Bourdeauducq 4e420fc297 flake: update inputs 2022-01-19 20:18:54 +08:00
Sebastien Bourdeauducq 5597be3356 flake: add beta to version string 2022-01-19 20:17:11 +08:00
Sebastien Bourdeauducq f542f045da manual: use git+https URL for ARTIQ flake 
github: flake URL lacks revCount
 2022-01-19 20:04:20 +08:00
Sebastien Bourdeauducq 53878fe1d4 flake: get version number from nix 2022-01-19 19:58:55 +08:00
Sebastien Bourdeauducq 735cd1eb3e manual: update development instructions 2022-01-14 16:50:08 +08:00
Steve Fan 3f812c4c2c
comm_kernel: fix RPC exception handling (#1801) 2022-01-12 15:23:37 +08:00
occheung b6c59a0cb3 update misoc dependencies 
Suppress warning when compiling libunwind.
7242dc5a41
 2022-01-11 17:32:19 +08:00
Steve Fan de5892a00a
comm_kernel: check if elements are within bounds for RPC list (#1824) 2022-01-11 17:16:45 +08:00
Peter Drmota 4eee49f889 gateware.test.suservo: Fix tests for python >=3.7 
Closes #1748
 2022-01-11 17:16:09 +08:00
occheung 9eee0e5a7b gateware/suservo: fix profile no. in test 
Follow-up/Test update for 9d49302.
 2022-01-11 14:20:47 +08:00
Steve Fan d7dd75e833 comm_kernel: fix off-by-one error for numeric value range check 2022-01-11 10:13:42 +08:00
Spaqin 095fb9e333
add Almazny support (#1780) 2022-01-11 09:55:39 +08:00
Sebastien Bourdeauducq 4e3e0d129c firmware: fix compilation warning 2022-01-11 09:31:26 +08:00
pca006132 12ee326fb4 firmware: fixed personality function 2022-01-11 09:30:19 +08:00
occheung 61349f9685 sinara_tester: fix outdated API 2022-01-10 17:23:28 +08:00
occheung cea0a15e1e suservo: use default urukul profile 2022-01-10 16:21:39 +08:00
occheung 8b45f917d1 urukul: use default profile 2022-01-10 16:21:39 +08:00
pca006132 6542b65db3 compiler: fixed exception codegen issues 2022-01-10 15:54:29 +08:00
pca006132 9f90088fa6 compiler: generate appropriate landingpad IR 
When used together with modified personality function, we got ~20%
performance improvement in exception unwinding with zynq.
 2022-01-10 15:54:29 +08:00
occheung 5e1847e7c1 compiler: rename `variables` to `retainedNodes` 
Part of the changes that was made to LLVM 6 by the time that LLVM 7 was released.
LLVM commit: 2c864551df
LLVM differential review: https://reviews.llvm.org/D45024
 2022-01-10 11:28:37 +08:00
occheung 6f3c49528d compiler: revert cabe5ac 
The lack of debug emitter causes #1821.
 2022-01-10 11:26:03 +08:00
Sebastien Bourdeauducq eaa1505c94 update documentation (#1820) 2022-01-08 11:55:52 +08:00
Leon Riesebos f42bea06a8 worker_db: removed warning for writing a dataset that is also in the archive 
Signed-off-by: Leon Riesebos <leon.riesebos@duke.edu>
 2022-01-08 11:48:18 +08:00
occheung 9d493028e5 gateware/suservo: write to profile 7 
Fixes #1817.
 2022-01-07 16:41:19 +08:00
Sebastien Bourdeauducq bbac477092 tools: fix importlib issue 2021-12-21 13:20:11 +08:00
Steve Fan c0a7be0a90 llvm_ir: move stacksave before lltag alloca in build_rpc 
Signed-off-by: Steve Fan <sf@m-labs.hk>
 2021-12-19 00:07:07 +00:00
Sebastien Bourdeauducq 9e5e234af3 stop using explicit ProactorEventLoop on Windows 
It is now the default in Python.
 2021-12-14 20:06:38 +08:00
Sebastien Bourdeauducq 352317df11 test_dataset_db: remove (too much breakage on Windows) 2021-12-14 19:27:15 +08:00
Sebastien Bourdeauducq a518963a47 test_dataset_db: disable tests broken on windows 2021-12-14 19:19:22 +08:00
Sebastien Bourdeauducq 37f14d94d0 test_dataset_db: fix for windows 2021-12-14 19:07:17 +08:00
Sebastien Bourdeauducq 4f723e19a6 RELEASE_NOTES: update 2021-12-14 00:05:49 +08:00
Peter Drmota 7c664142a5
Simplified use of the AD9910 RAM feature (#1584) 
* coredevice: Change Urukul default single-tone profile to 7

This allows using the internal profile control in RAM modulation mode (which always starts to play back at profile 0) without competing for the content of the profile 0 register used in single tone mode.

Signed-off-by: Peter Drmota <peter.drmota@physics.ox.ac.uk>

* ad9910/set_mu: comment on caveats when setting register

* ad9910: avoid unnecessary write/param

Credit: Solution proposed by @pmldrmota in https://github.com/m-labs/artiq/pull/1584#issuecomment-987774353

* revert 1064fdff (`set_mu()` comments)

158a7be7 had addressed this issue.

Co-authored-by: occheung <dc@m-labs.hk>
 2021-12-13 23:44:03 +08:00
Etienne Wodey 33a9ca2684 tools/file_import: use SourceFileLoader 
This allows loading modules from files with extensions not in
importlib.machinery.SOURCE_SUFFIXES

Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
 2021-12-09 11:47:04 +08:00
Sébastien Bourdeauducq 311a818a49
Merge pull request #1544 from airwoodix/dataset-compression 
datasets: support compression in HDF5 archives
 2021-12-06 12:43:19 +08:00
Sébastien Bourdeauducq 1def0d98c5
Merge branch 'master' into dataset-compression 2021-12-06 12:40:30 +08:00
Leon Riesebos 7ffe4dc2e3 coredevice: set default pow for ad9912 set_mu() 2021-12-06 12:34:55 +08:00
Leon Riesebos 9e3ea4e8ef coredevice: fixed type annotations for AD9910 2021-12-06 12:34:55 +08:00
Sebastien Bourdeauducq 12512bfb2f flake: get rid of TARGET_AR 2021-12-05 14:37:09 +08:00
Steve Fan 4a6bea479a
Host report for async error upon kernel termination (#1791) 
Closes #1644
 2021-12-04 13:33:24 +08:00
Sebastien Bourdeauducq 9bbf7eb485 flake: use ed25519 key for hitl 2021-12-03 18:35:10 +08:00
mwojcik f8a649deda release notes: mention 100mhz support 2021-12-03 17:19:11 +08:00
mwojcik 7953f3d705 kc705: add drtio 100mhz clk switch 2021-12-03 17:19:11 +08:00
mwojcik f281112779 satman: add 100mhz si5324 settings 
siphaser: add calculated vco for 100mhz comment
 2021-12-03 17:19:11 +08:00
mwojcik eec3ea6589 siphaser: add support for 100mhz rtio 2021-12-03 17:19:11 +08:00