whitequark
f2a6110cc4
Add integration tests for every language construct.
2015-07-22 18:34:52 +03:00
0b10f72c2b
Merge branch 'master' of https://github.com/m-labs/artiq
2015-07-22 10:44:49 +08:00
whitequark
dff4ce7e3a
Return LLVM IR module from LLVMIRGenerator.process.
2015-07-22 04:13:04 +03:00
whitequark
986d9d944f
Add artiq.compiler.testbench.run.
2015-07-22 04:10:15 +03:00
whitequark
86e006830c
Use the correct printf format for 64-bit integers.
2015-07-22 03:05:15 +03:00
whitequark
236d5b886a
Add support for Assert.
2015-07-22 02:58:59 +03:00
073e09ed36
gui: common format for results/params
2015-07-22 06:01:09 +08:00
bd2bd68a54
gui,client: do now show arguments
2015-07-22 05:47:14 +08:00
8402f1cdcd
master,gui: basic log support
2015-07-22 05:13:50 +08:00
e247fb5415
gui/tools: add ListSyncModel
2015-07-22 05:13:46 +08:00
whitequark
5d518dcec6
Require boolean operand in BoolOp.
2015-07-21 23:46:22 +03:00
whitequark
e21829ce74
Require boolean condition in If, While, IfExp.
2015-07-21 23:39:22 +03:00
whitequark
1e851adf4f
Add a polymorphic print function.
2015-07-21 22:32:10 +03:00
179ca36d09
gui: basic scan support
2015-07-21 21:24:24 +02:00
whitequark
0e7294db8d
Null-terminate all string literals.
2015-07-21 19:57:18 +03:00
whitequark
9d20080624
Use internal linkage for interior Python global values.
2015-07-21 19:55:43 +03:00
whitequark
8c9d9cb5a1
Make compiler.testbench.llvmgen emit a main() function.
2015-07-21 19:48:44 +03:00
whitequark
7301a76d68
Mark string constants as unnamed_addr.
...
As a result they will be merged when possible.
2015-07-21 17:10:31 +03:00
whitequark
49ece6a12a
Add support for string literals.
2015-07-21 14:27:48 +03:00
whitequark
64d2604aa8
Tolerate assertion failures in tests when looking for diagnostics.
2015-07-21 14:12:27 +03:00
whitequark
ec9d40b04f
Add LLVM IR generation for function calls.
2015-07-21 13:45:27 +03:00
whitequark
e299801c0f
LocalAccessValidator: fix validation of closures with no outer variables.
2015-07-21 13:16:18 +03:00
whitequark
6f11fa6bb1
Add conversion to LLVM IR (except handling of exception handling).
2015-07-21 04:55:01 +03:00
47191eda91
dds monitor: relax timing (for pipistrello)
2015-07-19 21:36:51 -06:00
1a0dc499dd
gui: exit when main window is closed
2015-07-19 18:27:41 +02:00
bb05ed268e
language/scan: add argument processor
2015-07-19 16:47:35 +02:00
whitequark
c6cd318f19
Fix artiq.compiler.ir.BasicBlock.__repr__.
2015-07-19 16:32:33 +03:00
937ca853aa
language/scan: fix random scan, add explicit scan, specify what runs on host/device
2015-07-19 11:36:52 +02:00
whitequark
7e3f91c0bb
Teach closures to LocalAccessValidator.
2015-07-19 12:08:26 +03:00
whitequark
2c010b10ee
Remove UnaryOp ARTIQ IR instruction; rename BinaryOp to Arith.
...
Everything it can express can also be expressed via Arith.
2015-07-19 11:51:53 +03:00
whitequark
ac491fae47
Add LocalAccessValidator.
2015-07-19 11:44:51 +03:00
whitequark
adf18bb042
Fix assignment to tuples in IRGenerator.
2015-07-19 10:31:11 +03:00
whitequark
4bd83fb43d
Use ".k" instead of "k" for the finalizer continuation variable.
...
The dot signifies that this is an internal variable and it
does not need to be tracked as if it was a user-defined one.
2015-07-19 10:30:42 +03:00
whitequark
8eedb3bc44
Fix IRGenerator.append(loc=...).
2015-07-19 10:29:33 +03:00
whitequark
f212ec0263
Add a trivial dead code elimination transform.
...
Its purpose is to sweep up basic blocks with no predecessors,
which are annoying to handle explicitly elsewhere.
2015-07-19 10:29:14 +03:00
whitequark
603d49dffa
Add a dominator analysis.
2015-07-18 20:48:52 +03:00
whitequark
224a93fde3
Make compiler.ir.BasicBlock.predecessors much faster.
2015-07-18 20:48:11 +03:00
deaa492566
language: add scan iterators
2015-07-18 19:26:41 +02:00
9e29a4650a
environment,gui: more argument types
2015-07-18 16:25:08 +02:00
5f95a302e6
environment: improve docstrings
2015-07-18 16:24:37 +02:00
657f198cdc
gui: display '---' on failed number result
2015-07-18 10:26:47 +02:00
whitequark
47cbadb564
Revert "Ensure bindings are created in correct order for e.g. "x, y = y, x"."
...
This reverts commit bcd1832203
2015-07-18 09:54:11 +03:00
whitequark
8e1cc8d985
Add an explicit ARTIQ IR instruction to create a closure.
2015-07-18 09:27:34 +03:00
whitequark
5ad02d5282
Fix ARTIQ IR generation for variables declared global.
2015-07-18 09:10:41 +03:00
whitequark
21eafefd28
Fix inference for globals.
2015-07-18 08:13:49 +03:00
whitequark
0d66bdfbf8
Fix For miscompilation.
2015-07-18 07:58:43 +03:00
whitequark
dde2e67c3f
Add source locations to ARTIQ IR instructions.
2015-07-18 07:49:42 +03:00
whitequark
255ffec483
Generate more compact ARTIQ IR for else-less if.
2015-07-18 07:49:27 +03:00
dd7920f0c3
gui: basic argument support
2015-07-17 21:28:46 +02:00
whitequark
e96bc3c36c
Add complete IR generator.
2015-07-17 21:29:06 +03:00
2576036ba1
language,worker: preserve order of arguments
2015-07-17 19:32:38 +02:00
6b36d93cc2
master,client: support repository rescan
2015-07-17 18:55:48 +02:00
4907991ea3
sync_struct: docstring cleanup
2015-07-17 18:53:43 +02:00
whitequark
f28549a11a
Add builtins.is_exception.
2015-07-17 16:05:02 +03:00
whitequark
3b661b2b65
Fix environment corruption by ExceptHandler without a name.
2015-07-17 16:04:46 +03:00
39c6bc940c
coreconfig: use new database API ( closes #75 )
2015-07-17 10:49:55 +02:00
9649e1837a
gui: basic plotting
2015-07-16 20:52:53 +02:00
a83473a19a
sync_struct: clarify notify_cb doc
2015-07-16 20:52:27 +02:00
whitequark
2dcb744519
Fix inference for default arguments.
2015-07-16 17:26:31 +03:00
whitequark
f8e51e07d5
Add zero/one accessors to TBool, TInt, TFloat.
2015-07-16 16:03:24 +03:00
whitequark
bcd1832203
Ensure bindings are created in correct order for e.g. "x, y = y, x".
2015-07-16 15:59:59 +03:00
whitequark
5756cfcebc
Correctly infer type of list(iterable).
2015-07-16 15:35:46 +03:00
whitequark
6cda67c0c6
Ensure type comparisons see through type variables.
2015-07-16 14:59:05 +03:00
whitequark
c1e7a82e97
Add IndexError and ValueError builtins.
2015-07-16 14:58:40 +03:00
whitequark
b58fa9067d
Add attributes to TRange.
...
Also make attributes an OrderedDict, for stable order during
LLVM IR generation.
2015-07-16 14:57:44 +03:00
whitequark
a6950bf11d
Move builtin.is_{builtin,exn_constructor} to types.
2015-07-16 14:56:39 +03:00
whitequark
5000f87dfc
Rename the field of CoerceT from expr to value.
2015-07-16 14:55:23 +03:00
whitequark
e9416f4707
Convert Slice into typed SliceT.
2015-07-16 14:54:04 +03:00
whitequark
53fb03d1bf
Restrict comprehensions to single for and no if clauses.
2015-07-16 14:52:41 +03:00
whitequark
227f97f8a3
Add inference for Index, Slice and ExtSlice.
2015-07-16 04:22:41 +03:00
66940ea815
rtio: disable NOP suppression after reset and underflow
2015-07-15 20:54:55 +02:00
f836465585
coredevice: environment -> runtime
2015-07-15 11:20:41 +02:00
84de2fb28b
expid: experiment -> class_name
2015-07-15 11:08:12 +02:00
255aba9247
test/worker: remove stale handler
2015-07-15 11:07:48 +02:00
7de56666e3
worker,environment: support scanning of arguments with no default
2015-07-15 10:59:48 +02:00
9ed4dcd7d1
repository: load experiments in worker, list arguments
2015-07-15 10:54:44 +02:00
whitequark
c724e024ce
Fix inference for multiple-target assignments.
2015-07-15 06:33:44 +03:00
7770ab64f2
worker: factor timeouts
2015-07-14 23:43:08 +02:00
whitequark
9ff9f85f19
Add accessors to instructions.
2015-07-14 22:18:38 +03:00
e20b260117
gui: fix selections
2015-07-14 19:08:08 +02:00
21e8596d8c
gui: RT results overview
2015-07-14 17:31:18 +02:00
55cd41444e
gui/DictSync: better support of nested structs
2015-07-14 17:30:55 +02:00
1edeb5a13f
sync_struct: docstring cleanup
2015-07-14 17:30:21 +02:00
84e7f55df3
gui: fix DDS class recognition
2015-07-14 17:28:26 +02:00
Yann Sionneau
6e3fd591f7
gui: remove unnecessary QSplitter
2015-07-14 16:59:04 +02:00
whitequark
bdcb24108b
Add basic IR generator.
2015-07-14 08:56:51 +03:00
whitequark
f417ef31a4
Make binop coercion look through CoerceT nodes.
...
This fixes inference for "x = 1 + 1" after int monomorphization.
2015-07-14 06:42:09 +03:00
Yann Sionneau
90ba9f7bbf
llvmlite: rename our package to be llvmlite_or1k to avoid collision with llvmlite package needed for numba
2015-07-14 01:01:56 +02:00
56fc7a484c
TTLInOut: timestamp -> timestamp_mu
2015-07-13 23:21:29 +02:00
820ff2da2c
test/coredevice: WA for lack of constant string support in compiler (see issue #68 )
2015-07-13 22:22:26 +02:00
32d141f5ac
refactor ddb/pdb/rdb
2015-07-13 22:21:32 +02:00
whitequark
ebe243f8d9
Add printing of SSA functions.
2015-07-13 21:08:20 +03:00
whitequark
dbdd45acc5
Add missing return.
2015-07-13 20:52:55 +03:00
whitequark
7c9afcce85
Fix Python default argument fiasco.
2015-07-13 20:52:48 +03:00
8b02b58a77
sync_struct/Notifier: do not pass root param to publish
2015-07-13 17:12:59 +02:00
0e92cfe053
artiq_run: remove support for stale watchdog API
2015-07-11 22:26:37 +02:00
whitequark
7c52910dc5
Add a basic SSA IR.
2015-07-11 18:46:37 +03:00
80eea4ce6c
test: relax test_time_keeps_running
...
on pipistrello this takes about 200-250ms
2015-07-09 16:30:37 -06:00
9d4073ef36
master: remove simple parameter history
2015-07-09 13:54:38 +02:00
96a5d73c81
worker: split build stage from prepare
2015-07-09 13:18:12 +02:00
34aacd3c5f
complete AD9914 support (no programmable modulus, untested)
2015-07-08 17:22:43 +02:00
Yann Sionneau
0109821078
tools: change asyncio_process_wait_timeout to handle cases where process.stdout is None. close #56
2015-07-07 19:30:36 +02:00
Yann Sionneau
2d343dd95d
pc_rpc: AsyncioClient __do_rpc coroutine was never yielded from
2015-07-07 19:26:47 +02:00
f3e5197c14
test/coredevice/test_time_keeps_running: remove unnecessary close_devices, upper bound
2015-07-07 15:48:47 +02:00
Yann Sionneau
706bf2b4b4
pxi6733: allow usage of 2-dimensional arrays. close #66
2015-07-07 15:42:08 +02:00
8a33d8c868
never stop RTIO counter
2015-07-07 15:29:38 +02:00
Yann Sionneau
df232f5405
lda driver: add error message when no device found
2015-07-07 15:18:28 +02:00
f9d878119a
pxi6733: add mediator
2015-07-05 19:07:57 +02:00
2bc8286f3f
pdq2/mediator: fix arm
2015-07-05 19:07:31 +02:00
58c0150822
ttl: improve clockgen doc
2015-07-05 19:07:13 +02:00
2eeaa3b9be
pxi6733: clean up docstring
2015-07-05 18:50:16 +02:00
a3fe538067
test: fix get_from_ddb
2015-07-04 22:36:23 -06:00
409c66e966
test: convert lda/tcube/409b to hardware_testbench
2015-07-04 21:44:28 -06:00
6faa8ecd51
test: split full_stack into coredevice and coredevice_vs_host
...
also adapt it to hardware_testbench
closes : #62
2015-07-04 20:35:02 -06:00
4cbf280f1a
test: return experiment not, rdb
2015-07-04 20:05:11 -06:00
00b9368a0c
language/core: add EncodedException to __all_
2015-07-04 19:51:30 -06:00
380f498284
Merge branch 'namespace_all'
...
* namespace_all:
use __all__ to structure the namespace
2015-07-04 18:38:26 -06:00
65ec6c28f4
ttl/clockgen: expose acc_width
2015-07-04 19:21:25 +02:00
abd58667b9
pxi6733: small cleanup
2015-07-04 18:49:09 +02:00
504576de58
remove unneeded import
2015-07-04 18:43:07 +02:00
753d61b38f
complete support for TTL clock generator
2015-07-04 18:36:01 +02:00
a615a3830a
test/coredevice: minor fixes
2015-07-04 18:35:11 +02:00
whitequark
549c110e7c
Fix types.TFunction.fold.
2015-07-04 04:27:24 +03:00
whitequark
4785f0a2de
Don't error out in inferencer if builtin arguments have polymorphic types.
2015-07-04 04:27:15 +03:00
whitequark
16432d2652
Implement escape analysis.
2015-07-04 04:16:37 +03:00
whitequark
4358c5c453
Unbreak return type inference.
2015-07-04 02:23:55 +03:00
whitequark
561d403ddd
Add missing _loc forwarding.
2015-07-04 00:59:03 +03:00
whitequark
ee0990cb5e
Automatically infer return type of NoneType for no return statements.
2015-07-04 00:58:48 +03:00
2674ed1d2d
use __all__ to structure the namespace
2015-07-02 22:02:21 -06:00
whitequark
bfabca494b
Remove regions from types.
...
Unification-based inference for regions is useful with a language
that has let bindings (which would propagate the regions) and
functions polymorphic over regions. For reasons of simplicity,
ARTIQ has neither, and making unification-based inference work would
essentially mean adding region coercions between most AST nodes,
and having every source subexpression have its own region variable,
with the appropriate subtyping relationship.
It's simpler to just keep that state outside of typedtree.
2015-07-02 22:55:12 +03:00
whitequark
0ae13ac1b9
Style fixes.
2015-07-02 22:38:55 +03:00
whitequark
7c833f0727
Move transforms.MonomorphismChecker to validators.MonomorphismValidator.
2015-07-02 21:54:31 +03:00
whitequark
02b41ea0f7
Add MonomorphismChecker.
2015-07-02 21:28:26 +03:00
whitequark
73a8f3c442
Fix tests.
2015-07-02 20:06:43 +03:00
whitequark
8a65266f14
Improve builtin call error message.
2015-07-02 20:06:07 +03:00
whitequark
196acb37f6
Add IntMonomorphizer.
2015-07-02 19:57:27 +03:00
whitequark
7ce9bdf54d
Move transforms to artiq.compiler.transforms, add artiq.Module.
2015-07-02 19:35:35 +03:00
2881d5f00a
gateware: add RTIO clock generator
2015-07-02 18:20:26 +02:00
whitequark
1702251ee5
Add region field to types.
2015-07-02 18:44:09 +03:00
whitequark
86cdc84f7e
Initialize types.TBuiltin's attributes field.
2015-07-02 18:19:01 +03:00
74f07092c7
test/coredevice: fix timestamp conflict
2015-07-02 10:26:00 +02:00
771ad6cb26
test/coredevice: adapt to MU API
2015-07-01 22:34:49 +02:00
5ace0f8e7a
Merge branch 'master' of https://github.com/m-labs/artiq
2015-07-01 22:23:10 +02:00
9d6287a6a3
expose machine units to user
2015-07-01 22:22:53 +02:00
Yann Sionneau
d7ef885d9e
controllers: print+exit instead of raising exception for argparse error, better doc for --simulation
...
As long as you use --simulation, the driver will be in simulation mode.
Even if you specify a --device or --channels.
That can allow you to just switch to simulation mode by adding
--simulation in the device database without having to
remove the serial number or device path/name.
2015-07-01 11:54:28 +02:00
Yann Sionneau
652f3359a2
lda_controller: fix typo
2015-07-01 11:41:01 +02:00
Yann Sionneau
ffe1355b1a
lda_controller: improve help message for --device argument
2015-06-29 19:24:55 +02:00
Yann Sionneau
a73776bd72
controllers: enforce the usage of either --simulation or --device
2015-06-29 19:21:32 +02:00
whitequark
6bf95397d7
Rename package py2llvm to compiler.
...
Since the package implements a typechecker along with a code generator,
and the typechecker will be run before or together with transformations,
this name is more descriptive.
2015-06-29 20:15:22 +03:00
Yann Sionneau
515aa96819
controllers: use --simulation for simulation
2015-06-29 13:04:01 +02:00
