David Nadlinger
280915d54f
coredevice/suservo: Adjust T_CYCLE to match gateware
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See GitHub #1338 .
2019-07-17 00:20:22 +01:00
f7e10759dc
suservo: note requirement to stop servo when accessing state
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As already mentioned in the gateware.
One alternative would be to detect address collisions and
stall the read for one cycle.
Note that there will in general not be a consistent view of the servo
state unless the servo is stopped.
close #1337
2019-07-08 18:37:42 +02:00
David Nadlinger
8bf9640185
coredevice/suservo: Fix output IIR state width in docstring
2019-06-21 11:27:39 +02:00
David Nadlinger
34f48f57cc
coredevice/suservo: Fix {get,set}_y_mu() scaling
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Previously, Channel.set_y(1) would set the output to -1 instead.
2019-06-21 11:27:39 +02:00
74e4b01201
urukul: document consequences of incorrect CPLD clock settings
2019-06-11 11:12:12 +08:00
adf3df2bb5
suservo coredevice driver: mask ftw to avoid erroneous sign extension
2019-06-03 21:40:04 +02:00
David Nadlinger
fc95183e04
coredevice: Fix host-side serialization of (nested) lists
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Test case to follow.
2019-03-31 17:10:27 +01:00
d07c6fcfea
ad9910: handle unprogrammed EEPROM and numpy corner cases
2019-03-22 14:28:47 +08:00
04e0c23e78
ad9910: support reading synchronization values from EEPROM
2019-03-13 15:34:47 +08:00
964a349a19
add Kasli I2C driver
2019-03-13 15:33:50 +08:00
227c729f56
fix permissions
2019-03-11 20:43:28 +08:00
aee8965897
ad9910: add ram conversion tooling and unittests
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-02-21 15:59:52 +00:00
b57cad77ad
ad9910: make ram read work for short segments
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also cleanup and style
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-02-21 14:47:58 +00:00
hartytp
0ebff04ad7
SUServo: apply bit masks to servo memory writes to prevent overflows
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Signed-off-by: TPH <thomas.harty@physics.ox.ac.uk>
2019-02-07 17:04:11 +01:00
hartytp
f6142816b8
Revert "SUServo: remove references to non-existent a0 parameter" ( #1270 )
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This reverts commit f3aab2b891
2019-02-07 15:57:43 +00:00
hartytp
fe63c9b366
SUServo: remove references to non-existent a0 parameter ( #1268 )
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Signed-off-by: Thomas Harty <thomas.harty@physics.ox.ac.uk>
2019-02-07 15:29:32 +00:00
hartytp
df6c1fca2c
SUServo: flake8 [NFC] ( #1267 )
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Signed-off-by: Thomas Harty <thomas.harty@physics.ox.ac.uk>
2019-02-07 15:13:44 +00:00
8c5a502591
ad53xx: ignore F3 (reserved)
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-24 15:50:46 +01:00
330c5610e9
ad9912: fix imports
2019-01-23 17:59:08 +08:00
b692981c8e
ad9910: add note about red front panel led
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-22 12:49:42 +01:00
91e375ce6a
ad9910: don't reset the input divide-by-two
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suspected of causing weird PLL lock timout errors
https://freenode.irclog.whitequark.org/m-labs/2019-01-22#1548148750-1548143221 ;
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-22 09:37:20 +00:00
81ff3d4b29
ad9912: add some slack after init
2019-01-21 17:10:58 +00:00
84f7d006e8
ad9910: add precision about tune_io_update_delay/tune_sync_delay order
2019-01-21 19:40:55 +08:00
30051133b7
urukul: fix typos
2019-01-21 19:40:55 +08:00
40187d1957
ad9910: support configurable refclk divider and pll bypass
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for #1248
* also always keep refclk input divider (by two) reset
2019-01-18 12:23:53 +00:00
385916a9a4
ad9912: support configurable clk_div
2019-01-18 12:16:08 +00:00
2bea5e3d58
urukul: support configurable refclk divider
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for #1248
2019-01-18 12:09:32 +00:00
David Nadlinger
a565f77538
Add gateware input event counter
2019-01-15 10:55:07 +00:00
David Nadlinger
6c52359e59
coredevice: Add _mu suffix to AD991x ref_time arguments
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GitHub: Fixes #1243 .
2019-01-12 17:34:35 +00:00
whitequark
49682d0159
Improve Python 3.7 compatibility.
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async is now a full (non-contextual) keyword.
There are two more instances:
- artiq/frontend/artiq_client.py
- artiq/devices/thorlabs_tcube/driver.py
It is not immediately clear how to fix those, so they are left for
later work.
2019-01-12 13:17:59 +00:00
David Nadlinger
48fc175a6b
coredevice.ttl: More imperative mood in docstrings [nfc]
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This follows Python conventions (PEP257) and unifies the style with
other comments.
2019-01-12 12:01:55 +00:00
David Nadlinger
3e84ec2bf1
coredevice.ad9910: Fix phase tracking ref_time passing
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This is difficult to test without hardware mocks or some
form of phase readback, but the symptom was that e.g.
`self.dds.set(…, ref_time=now_mu() - 1)` would fail
periodically, that is, whenever bit 32 of the timestamp
would be set (which would be turned into the sign bit).
This is a fairly sinister issue, and is probably a compiler
bug of some sort (either accepts-invalid or wrong type inference).
2019-01-12 00:47:38 +00:00
101671fbbf
core_analyzer: support uniform VCD time intervals
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close #1236
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-10 19:35:09 +01:00
19748fe495
ad9910: fix RTIO fine timestamp nudging
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Previously the TSC was truncated to an even coarse RTIO periods before doing
the setting SPI xfer. Afterwards the the IO update pulse would introduce
at least one but less than two RTIO cycles. Ultimately the RTIO TSC was
truncated again to even. If the SPI xfer takes an odd number of RTIO
periods, then a subsequent xfer would collide.
close #1229
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-09 17:22:57 +00:00
b25ab1fc88
ad9910: add more slack in tune_sync_delay
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close #1235
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-09 16:07:31 +00:00
Drew
40370c4d45
Docs: fix build warnings ( #1234 )
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* ad9910: finish CONT_RECIRCULATE -> CONT_RAMPUP
Found while building docs. Forgot to refactor strings.
Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
* spi2: reformat update_xfer_duration_mu docstring
update_xfer_duration_mu docstring threw warning while building docs,
didn't use consistent indent in warning.
Signed-off-by: Drew Risinger <drewrisinger@users.noreply.github.com>
2019-01-09 11:39:23 +08:00
David Nadlinger
4fb434674d
coredevice: Fix ad9910 __all__ exports
2019-01-08 18:55:26 +00:00
David Nadlinger
cadde970e1
urukul: Expand CPLD sync_sel explanation [nfc]
2019-01-08 02:37:58 +00:00
David Nadlinger
7bcdeb825b
ad9910: Add inverse FTW/ASF conversions
2019-01-08 02:18:14 +00:00
David Nadlinger
4d793d7149
ad9910: Truncate phase word to 16 bits
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This avoids overflowing into the asf portion of the register.
2019-01-08 02:18:14 +00:00
a7d4d3bda9
ad9910: CONT_RECIRCULATE -> CONT_RAMPUP
2018-12-17 13:25:00 +00:00
35bdf26f01
Merge branch 'ad9910-ram'
2018-12-17 21:16:44 +08:00
David Nadlinger
e608d6ffd3
coredevice, firmware: Add rtio_input_timestamped_data
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Integration tests to follow as part of an RTIO counter phy that
makes use of this.
2018-12-15 00:35:04 +00:00
79eadb9465
ad9910: add RAM mode methods
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* also refactor the CFR1 access into a method
c.f. #1154
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-11 14:54:16 +00:00
efd400b02c
ad9910: style [nfc]
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-11 11:36:25 +01:00
d90eb3ae88
ad9910: add read64()
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-07 21:27:00 +00:00
baf88050fd
urukul: expand attenuator HITL unittests
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* read back with cleared backing state
* individual channel settings
* check backing state
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-07 21:06:12 +00:00
dce4f036db
grabber: work around windows numpy int peculiarity (same as a81c12de9)
2018-11-30 18:41:14 +08:00
450a035f9e
suservo: move overflowing RTIO address bits into data
2018-11-26 06:54:20 +08:00
b32e89444c
Merge branch 'master' into new
2018-11-26 01:02:19 +08:00
a81c12de94
urukul: work around windows numpy int peculiarity
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"OverflowError: Python int too large to convert to C long" otherwise
opticlock#74
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-25 16:56:45 +01:00
8f9858be4c
ad9914: remove automatic continuous phase compensation (like Urukul)
2018-11-19 22:00:20 +08:00
53e79f553f
Merge branch 'master' into new
2018-11-19 11:54:50 +08:00
a3e0b1c5b4
ad9914,spi2: add warnings about driver state and DMA. Closes #1113
2018-11-17 22:10:20 +08:00
69e699c7bd
ttl: compensate for SED latency in input gating
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Closes #1137
2018-11-17 22:10:20 +08:00
3ad68f65c5
urukul: make get_att_mu() not alter state
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-16 14:56:26 +00:00
d1eee7c0ea
ad9910: ensure sync is driven when required
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close #1194
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-16 13:21:01 +00:00
1b841805f6
Merge branch 'master' into new
2018-11-16 15:20:32 +08:00
c3178c2cab
ad9910: profile support
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-14 08:30:28 +01:00
d0cadfeb4b
ad9910: more idiomatic register names
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-14 07:55:01 +01:00
a52d1be140
urukul: expose PROFILE setting
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* add documentation
* add unittest
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-14 07:43:56 +01:00
a4997c56cf
ad9910: simplify edge detection logic
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 18:54:34 +00:00
14b6b63916
ad9910: rewire io_delay tuning
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This now reliably locates the SYNC_CLK-IO_UPDATE edge by doing two
scans at different delays between start and stop IO_UPDATE.
It also works well when one delay is very close to the edge.
And it correctly identifies which (start or stop) pulse hit or crossed
the SYNC_CLK edge.
for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 18:38:27 +00:00
38c6878d49
urukul: mention min/max attenuation
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 13:32:05 +01:00
e565ca6b82
urukul: slow down att write to datasheet limit
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 13:23:06 +01:00
998be50f07
urukul: handle MSB in att_reg
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 13:21:14 +01:00
c990b5e4f1
Merge remote-tracking branch 'origin/master' into new
2018-11-08 20:21:56 +08:00
0bee43aa58
sawg: use new rtio_output() API
2018-11-08 20:16:30 +08:00
bec25cbaa0
suservo: use new rtio_output() API
2018-11-08 20:13:14 +08:00
e8d58b35b4
spi2: use new rtio_output() API
2018-11-08 20:12:30 +08:00
d18546550e
grabber: use new rtio_output() API
2018-11-08 19:15:50 +08:00
2549e623c1
ad9914: use new rtio_output() API
2018-11-08 19:15:44 +08:00
8caea0e6d3
gateware,runtime: optimize RTIO kernel interface further
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* now pinning (TODO: atomicity)
* for inputs, merge request and timeout registers
2018-11-08 18:29:24 +08:00
fae95e73ad
ttl: use optimized rtio_output API
2018-11-07 23:41:43 +08:00
3d0c3cc1cf
gateware,runtime: optimize RTIO output interface
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* reduce address to 8 bits
* merge core, channel and address into 32-bit pre-computable "target"
* merge we register into data register
2018-11-07 23:39:58 +08:00
e6efe830c4
ad9910: rewire sync delay tuning
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* search from wide window end
* decouple margins and minimum window size
* add note about kasli jitter
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-07 14:52:03 +00:00
ad0254c17b
Merge branch 'switching125' into new
2018-11-07 22:03:18 +08:00
6c00ab57c0
test_ad9910: relax SYNC window
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 19:31:38 +01:00
172633c7da
test_ad9910: default to a useful seed
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 17:35:57 +01:00
0b2661a34d
ad9910: robustify SYNC window finding
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don't integrate too long, find the window tip fast and early
a couple 100 SYNC pulses are sufficient
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 12:41:21 +00:00
31f68ddf6c
Merge branch 'urukul-sync'
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* urukul-sync: (29 commits)
urukul: flake8 [nfc]
ad9910: flake8 [nfc]
urukul/ad9910 test: remove unused import
test_urukul: relax speed
urukul,ad9910: print speed metrics
kasli: add PTB2 (external clock and SYNC)
kasli: add sync to LUH, HUB, Opticlock
kasli_tester: urukul0 mmcx clock defunct
test_ad9910: relax ifc mode read
tests: add Urukul-AD9910 HITL unittests including SYNC
ad9910: add init bit explanation
test: add Urukul CPLD HITL tests
ad9910: fiducial timestamp for tracking phase mode
ad9910: add phase modes
ad9910: fix pll timeout loop
tester: add urukul sync
ptb: back out urukul-sync
ad9910: add IO_UPDATE alignment and tuning
urukul: set up sync_in generator
ad9910: add io_update alignment measurement
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close #1143
2018-11-05 19:54:30 +01:00
6fb18270a2
urukul: flake8 [nfc]
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:45:24 +01:00
832690af9a
ad9910: flake8 [nfc]
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:44:51 +01:00
9fb850ae75
ad9910: add init bit explanation
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:02 +01:00
bc04da15c5
test: add Urukul CPLD HITL tests
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for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:00 +01:00
141cc7d99f
ad9910: fiducial timestamp for tracking phase mode
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:58 +01:00
2f6d3f79ff
ad9910: add phase modes
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* simplified and cross-referenced the explanation of the different
phase modes.
* semantically and functionally merged absolute and tracking/coherent
phase modes.
* simplified numerics to calculate phase correction
* added warning about possible inconsistency with DMA and default
phase mode
* restricted __all__ imports
* moved continuous/relative phase offset tracking from an instance
variable to a "handle" returned by set()/set_mu() in order to avoid
state inconsistency with DMA (#1113 #1115 )
for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:55 +01:00
d3ad2b7633
ad9910: fix pll timeout loop
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:53 +01:00
06139c0f4d
ad9910: add IO_UPDATE alignment and tuning
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for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:48 +01:00
1066430fa8
urukul: set up sync_in generator
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:46 +01:00
4bbd833cfe
ad9910: add io_update alignment measurement
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for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:44 +01:00
7b92282012
ad9910: add docs for sync tuning, refactor
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:42 +01:00
8a47a6b2fb
ad9910: disable sync_clk output
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:40 +01:00
65e2ebf960
ad9910: add sync delay control, auto tuning
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* expose multi device sync functionality
* sync delay configuration interface
* auto-tuning of sync delay from device_db seed
for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:37 +01:00
8dbf5f87fd
ad9910: simplify io_update pulsing on init, set_mu
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:35 +01:00
0b3b07a7da
ad9910: add power down method
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:34 +01:00
0433e8f4fe
urukul: add sync_in generator
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for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:30 +01:00
f62c1ff0bb
TTLClockGen: expose acc_width
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:27 +01:00
David Nadlinger
f79b9d9e1e
ttl: Expand input gate/count API docstrings
2018-11-03 20:33:19 +08:00
David Nadlinger
5d2e3f975f
coredevice: Add get_rtio_counter_mu() docstring [nfc]
2018-11-03 20:33:19 +08:00
