Commit Graph

711 Commits

Author SHA1 Message Date
a65239957f ad53xx: distinguish errors 2020-09-24 10:52:03 +02:00
c55f2222dc fastino: documentation and eem pass-through
* Repeat information about matching log2_width a few times
  in the hope that people read it. #1518
* Pass through log2_width in kasli_generic json. close #1481
* Check DAC value range. #1518
2020-09-22 17:58:53 +02:00
6195b1d3a0 rpc: fixed _write_bool
Closes #1519
2020-09-04 13:49:22 +08:00
56aa22caeb fastino: document/cleanup
* added documentation on `update`/`hold` mechanism
* mask machine unit values
* cleanup coredevice driver

close #1518
2020-09-03 17:44:26 +02:00
b2572003ac RPC: optimization by caching
This reduced the calls needed for socket send/recv.
2020-08-28 14:58:34 +08:00
7cf974a6a7 comm_kernel: fix typo 2020-08-28 12:25:23 +08:00
7181ff66a6 compiler: improved rpc performance for list and array
1. Removed duplicated tags before each elements.
2. Use numpy functions to speedup parsing.
2020-08-26 14:17:06 +08:00
David Nadlinger
8783ba2072 compiler/firmware: RPCs for ndarrays 2020-08-09 17:08:43 +01:00
David Nadlinger
9af6e5747d compiler: Factor rpc_tag() out of llvm_ir_generator 2020-08-09 03:54:41 +01:00
pmldrmota
1df62862cd
AD9910: Write correct number of bits to POW register (#1498)
* coredevice.ad9910: Add return type hints to conversion functions

* coredevice.ad9910: Make set_pow write correct number of bits
The AD9910 expects 16 bits. Thus, if writing 32 bits to the POW register, the chip would likely enter a locked-up state.

* coredevice.ad9910: Correct data alignment in write_16

Co-authored-by: Robert Jördens <rj@quartiq.de>

* coredevice.ad9910: Add function to read from 16 bit registers

Co-authored-by: drmota <peter.drmota@physics.ox.ac.uk>
Co-authored-by: Robert Jördens <rj@quartiq.de>
2020-08-07 10:10:44 +02:00
2a2f5c4d58 comm_analyzer: make header error flag more general 2020-07-20 19:39:19 +08:00
charlesbaynham
2429a266f6
ad9912: Fix typing problem on ad9912 (#1466)
Closes #1463

FTW and phase word were ambiguously typed, resulting in failure to compile
2020-06-16 20:17:22 +02:00
9822b88d9b
ad9910: fix asf range (#1450)
* ad9910: fix asf range

The ASF is a 14-bit word. The highest possible value is 0x3fff, not
0x3ffe. `int(round(1.0 * 0x3fff)) == 0x3fff`.

I don't remember and understand why this was 0x3ffe since the beginning.
0x3fff was already used as a default in `set_mu()`

Signed-off-by: Robert Jördens <rj@quartiq.de>

* RELEASE_NOTES: ad9910 asf scale change

Co-authored-by: David Nadlinger <code@klickverbot.at>
2020-05-29 11:13:26 +02:00
2538840756
Coredevice Input Validation (#1447)
* Input validation and masking of SI -> mu conversions (close #1446)

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* Update RELEASE_NOTES

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

Co-authored-by: Robert Jördens <rj@quartiq.de>
2020-05-17 15:09:11 +02:00
b3b6cb8efe
ad53xx improvements (#1445)
* ad53xx: voltage_to_mu() validation & documentation (closes #1443, #1444)
The voltage input (float) is checked for validity. If we need more
speed, we may want to check the DAC-code for over/underflow instead.

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* ad53xx documentation: voltage_to_mu is only valid for 16-bit DACs

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* AD53xx: add voltage_to_mu method (closes #1341)

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* ad53xx: improve voltage_to_mu performance
Interger comparison is faster than floating point math.

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* AD53xx: voltage_to_mu method now uses attribute values

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* Fixup RELEASE_NOTES.rst

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>

* ad53xx: documentation improvements

voltage_to_mu return value
14-bit DAC support

Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
2020-05-08 19:23:43 +02:00
e8b73876ab comm_kernel: add Zynq runtime identifier 2020-04-12 17:25:14 +08:00
de57039e6e comm_kernel: cleanup 2020-04-12 16:02:36 +08:00
9dc24f255e comm_kernel: remove dead code 2020-04-12 15:06:46 +08:00
e803830b3b fastino: support wide RTIO interface and channel groups 2020-03-05 17:55:04 +00:00
8451e58fbe ad9912: fix ftw width docstring 2020-02-27 02:11:12 +08:00
248230a89e fastino: style 2020-01-20 13:25:00 +01:00
c45a872cba fastino: fix init, set_cfg 2020-01-20 13:25:00 +01:00
2c4e5bfee4 fastino: add [WIP] 2020-01-20 13:25:00 +01:00
e427aaaa66 basemod_att: fix imports 2020-01-20 20:14:24 +08:00
7ab0282234 adf5355: style 2020-01-20 13:13:08 +01:00
9368c26d1c mirny: add to manual 2020-01-20 13:13:08 +01:00
01a6e77d89 mirny: add
* This targets unrelease CPLD gateware (https://github.com/quartiq/mirny/issues/1)
* includes initial coredevice driver, eem shims, and kasli_generic tooling
* addresses the ARTIQ side of #1130
* Register abstraction to be written

Signed-off-by: Robert Jördens <rj@quartiq.de>
2020-01-20 13:13:08 +01:00
833f428391 sayma: fix hmc542 to/from mu 2020-01-16 09:10:32 +08:00
David Nadlinger
1e864b7e2d coredevice/suservo: Add separate methods for setting only the IIR offset 2019-12-30 20:02:22 +00:00
b5e1bd3fa2 coredevice: simplify/cleanup network connection code
This removes:
* host-side keepalive, which turns out not to be required
* custom connection timeout (the default is OK)
* SSH tunneling support (doesn't seem to be actually used anywhere)
2019-12-23 19:53:49 +08:00
David Nadlinger
af31c6ea21 coredevice: Don't use is to compare with integer literal
This works on CPython, but is not guaranteed to do so, and
produces a warning since 3.8 (see https://bugs.python.org/issue34850).
2019-12-22 05:46:41 +00:00
fb2076a026 basemod_att: add dB functions, document 2019-12-21 14:56:41 +08:00
d4e039cede basemod: add coredevice driver 2019-12-21 14:18:10 +08:00
8759c8d360 shiftreg: fix get method 2019-12-21 14:17:22 +08:00
cab8c8249e coredevice/shiftreg: add get method 2019-12-20 18:58:50 +08:00
gthickman
56d4b70e01 ad9910 osk (#1387)
* updated adoo10.py for RAM mode frequency control

* updated docstrings for set_cfr1() in ad9910.py

* fixed typo in ad9910.py

* added docstrings to ad9910.py

* removed OSK-related changes in AD9910, to be included in a separate branch.

* updated AD9910 set_cfr1 for control of OSK mode parameters

* updated AD9910 set_cfr1() for control of OSK mode parameters.
2019-11-18 15:57:26 +01:00
Fabian Schmid
f73e2a3d30 doc: clarify urukul attenuator behavior
Closes #1386

Signed-off-by: Fabian Schmid <fabian.schmid@mpq.mpg.de>
2019-11-18 15:56:00 +01:00
Garrett
f8a7e278b8 removed OSK-related changes in AD9910, to be included in a separate branch. 2019-11-12 19:07:05 +01:00
Garrett
3a19ba7e62 added docstrings to ad9910.py 2019-11-12 19:07:05 +01:00
Garrett
4ad3651022 fixed typo in ad9910.py 2019-11-12 19:07:05 +01:00
Garrett
6d34eb3bb0 updated docstrings for set_cfr1() in ad9910.py 2019-11-12 19:07:05 +01:00
Garrett
61ca46ec3f updated adoo10.py for RAM mode frequency control 2019-11-12 19:07:05 +01:00
5279bc275a urukul: rework EEPROM synchronization. Closes #1372 2019-11-05 18:56:10 +08:00
1f15e55021 comm_analyzer: don't assume every message has data
close #1377
2019-10-28 15:35:44 +01:00
a8f85860c4 coreanalyzer: AD9914 fixes (#1376) 2019-10-17 07:29:33 +08:00
Tim Ballance
ada3b39f4e Fix ad9910 ram mode asf scale error in polar mode 2019-10-04 20:14:41 +02:00
Tim Ballance
448080e71d Fix ad9910 ram mode asf scale error
RAM mode amplitude to ASF conversion should be << 18 rather than << 16
2019-10-04 20:14:41 +02:00
98cd9a539c compiler: support Cortex A9 target 2019-08-26 10:46:22 +08:00
David Nadlinger
99e490f9ff coredevice/suservo: Slightly reword get_adc[_mu]() docstring for clarity
This hopefully suggests a bit better that the value is the last one
fetched by the servo (i.e. needs the servo active to update), rather
than somehow requesting a new sample to be taken.
2019-07-30 12:22:08 +01:00
b8870997d0 doc: clarify TTL direction control with buffered cards 2019-07-24 10:04:45 +08:00