d37577a8a1
rtio: add input collector module
2017-09-19 15:30:30 +08:00
6dc9cad2c9
rtio: add explanation about cri.counter
2017-09-19 12:05:12 +08:00
81d6317053
rtio/sed: take global fine TS width
2017-09-18 11:30:49 +08:00
65baca8c57
rtio: clean up error-prone rtlink.get_or_zero()
2017-09-17 16:11:36 +08:00
e2c1d4f3d5
rtio/sed: trigger collision error on non-data replace
2017-09-16 17:01:23 +08:00
0e25154e25
rtio/sed: quash writes to LogChannel
2017-09-16 15:19:30 +08:00
1cfe90b1d9
rtio/sed/Gates: fix fine_ts_width computation
2017-09-16 15:09:21 +08:00
a3bb6c167c
rtio: use SED
2017-09-16 14:13:42 +08:00
131f5e4a3b
rtio/sed/LaneDistributor: fix CRI address
2017-09-16 14:13:01 +08:00
a155a481b1
rtio/sed: add top-level core
2017-09-16 14:04:56 +08:00
92c63ce2e4
rtio/sed: rename fifos/gates, refactor tsc
2017-09-16 14:03:48 +08:00
ac52c7c818
rtio/sed/LaneDistributor: style
2017-09-16 14:02:37 +08:00
6b7a1893c7
rtio/sed/OutputDriver: support channels with different fine timestamp widths
2017-09-16 10:53:30 +08:00
f39ee7ad62
rtio/sed: fix seqn_width
2017-09-16 10:52:37 +08:00
064503f224
rtio/sed/LaneDistributor: support specifying existing CRI
2017-09-16 10:52:13 +08:00
1cb05f3ed5
rtio/sed/LaneDistributor: persist underflow/sequence error until next write
2017-09-16 10:51:44 +08:00
3c922463a0
style
2017-09-15 15:36:46 +08:00
8e5ab90129
rtio/sed: add FIFO wrapper
2017-09-15 15:36:34 +08:00
490c9815a2
rtio/sed: add TSC/gate (untested)
2017-09-14 19:53:21 +08:00
181cb42ba8
rtio/sed: centralize all layouts in one file
2017-09-14 19:52:31 +08:00
1b61442bc3
rtio/sed: fix lane spreading and enable by default
2017-09-13 22:48:10 +08:00
8cfe2ec53a
rtio/sed: fix sequence number width computation
2017-09-13 22:11:41 +08:00
a92a955d1e
rtio/sed: use __all__
2017-09-13 18:17:22 +08:00
c74abccfd5
rtio/sed: lane distributor fixes
2017-09-13 17:50:06 +08:00
bdd96084c5
rtio/sed: add lane distributor (untested)
2017-09-13 00:07:26 +08:00
00ff3f5b0d
rtio/sed: fix output driver busy output
2017-09-11 23:04:52 +08:00
666bc600a2
rtio/sed: add output driver (untested)
2017-09-11 11:10:28 +08:00
1d2ebbe60f
rtio/sed: make ON payload layout configurable, add latency function
2017-09-11 09:06:40 +08:00
c5d6a2ba1a
rtio/sed: more output network fixes
2017-09-10 23:41:04 +08:00
96505a1cd9
rtio/sed: output network fixes
2017-09-10 23:23:10 +08:00
5646e19dc3
rtio/sed: add output network (untested)
2017-09-10 14:38:43 +08:00
Florent Kermarrec
2910b1be5e
artiq/gateware/rtio/dma: replace leave_out with omit in Record.connect
2017-07-04 10:48:06 +02:00
838127d914
rtio: break DMA timing path
2017-07-02 10:24:01 +08:00
911ee4a959
rtio: make pipelined logic reset_less
...
* latency-corrected counters
* registered error logic
2017-06-29 12:55:32 +02:00
f520d4a768
rtio: undo _RelaxedAsyncResetSynchronizer
2017-06-28 22:08:15 +02:00
3cbbcdfe96
sawg: don't enable_replace for Config
...
closes #762
2017-06-28 20:31:40 +02:00
01847271c5
rtio: use reset_less signal for reset fanout
2017-06-28 19:43:55 +02:00
f4c6879c76
sawg: special case Config RTIO address
2017-06-22 10:26:29 +02:00
0d8067256b
rtio: refactor RelaxedAsyncResetSynchronizer
2017-06-18 14:37:08 +02:00
424b2bfbd8
rtio: describe rio and rio_phy domains a bit more
2017-06-17 12:21:07 +02:00
219dfd8984
rtio: add one register level for rio and rio_phy resets
...
* This should give Vivado some wiggle room during PnR.
* It needs three new clock domains which is ugly. But since
AsyncResetSynchronizer can only drive clock domains resets directly
there seems to be no other way to add one register level currently.
2017-06-17 12:17:48 +02:00
2a76034fbc
cri: add note about clearing of o_data
2017-06-16 19:06:00 +02:00
9ab63920e0
Remove Pipistrello support
...
Closes #658
Closes #381
2017-05-15 17:17:44 +08:00
c0100ebc56
rtio: fix indentation
2017-04-06 12:08:13 +08:00
207453efcd
rtio: add a missing case for collision reporting
2017-04-06 11:28:16 +08:00
whitequark
47632f81b1
gateware: CRIArbiter -> CRISwitch.
2017-04-05 16:10:39 +00:00
whitequark
391660e545
gateware: simplify the CRI arbiter to use a plain mux.
2017-04-05 15:09:19 +00:00
12249dac57
rtio: do not clear asynchronous error flags on RTIO reset
2017-04-03 00:20:30 +08:00
db3118b916
drtio: use BlindTransfer for error reporting
2017-04-03 00:18:07 +08:00
b74d6fb9ba
make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads
2017-03-27 16:32:23 +08:00
whitequark
4de336fbe9
gateware: reverse bytes of SDRAM word, not bits.
2017-03-17 11:16:46 +00:00
whitequark
6b63322106
gateware: reverse SDRAM words in RTIO DMA engine.
2017-03-17 07:29:28 +00:00
whitequark
4b14887ddb
gateware: work around ISE/Vivado bugs with very wide shifts.
2017-03-17 07:29:28 +00:00
a7de58b604
rtio: Inout → InOut
2017-03-14 14:18:55 +08:00
497c795d8c
drtio: input support (untested)
2017-03-13 23:54:44 +08:00
1e6a33b586
rtio: handle input timeout in gateware
...
The information passed by the runtime will be used by the DRTIO core
to poll the remote side appropriately.
2017-03-03 17:37:47 +08:00
d2f2415b50
analyzer: use CRI and connect at RTIO core
...
This causes DMA events to be included in analyzer traces.
2017-03-02 18:47:56 +08:00
7d6ebabc1b
reorganize core device communication code
2017-02-27 18:37:30 +08:00
c66efc0279
moninj: do not require a rsys clock domain
2017-02-20 15:52:48 +08:00
86f6b391b7
ad9xxx -> ad9_dds
2017-01-04 11:34:52 +01:00
6b998581cc
rtio: use same reset for counter_rtio whatever the interface delay is
2016-12-15 09:28:13 +08:00
8381db279f
sawg: wire up all HBF outputs, latency compensation in phys, simplify
2016-12-14 19:16:07 +01:00
6cdb96c5e0
rtio: add support for latency compensation in phy
...
* if multiple RTIO channels influence the same data stream and physical
output channel (see SAWG) differential latency needs to be compensated
* this is a NOP for phys with zero delay (default)
* if delay==1, it adds one timestamp-wide register
* if delay >1, it adds one adder and one register
* latency compensation using (~10-50 deep) delay lines is about as
expensive as a single adder+register but very tedious to implement
2016-12-14 19:16:07 +01:00
c63fa46430
Merge branch 'phaser2'
...
* phaser2: (157 commits)
sawg/hbf: tweak pipeline for timing
fir: register multiplier output
conda/phaser: build-depend on numpy
sawg: reduce coefficient width
sawg: fix latency
test/fir: needs mpl. don't run by default
test/sawg: patch spline
sawg: use ParallelHBFCascade to AA [WIP]
fir: add ParallelHBFCascade
fir: add ParallelFIR and test
gateware/dsp: add FIR and test
README_PHASER: update
sawg: documentation
sawg: extract spline
sawg: document
sawg: demo_2tone
sawg: round to int64
gateware/phaser -> gateware/ad9154_fmc_ebz
phaser: fix typo
sawg: merge set/set64
...
2016-12-12 17:31:39 +01:00
7196bc21c1
rtio: simplify error reset logic
...
Channel is always selected when reset is issued.
2016-12-12 17:35:10 +08:00
bc36bda94a
perform RTIO init on comms CPU side
2016-12-09 14:16:55 +08:00
f3c50a37ca
rtio: always read full DMA sequence
2016-12-06 01:05:47 +08:00
c413d95b49
rtio: fix DMA get_csrs
2016-12-05 18:12:09 +08:00
b677c69faf
rtio: fix handling of o_status in DMA
2016-12-05 18:01:48 +08:00
75ea13748a
rtio: fix DMA data MSB and stop signaling, self-checking unittest
2016-12-05 18:01:48 +08:00
a5834765d0
rtio: more DMA fixes, better stopping mechanism
2016-12-05 18:01:48 +08:00
30bce5ad35
rtio: DMA fixes
2016-12-05 18:01:48 +08:00
88ad054ab6
Merge branch 'drtio'
2016-12-03 23:25:17 +08:00
3931d8097b
rtio: fix DMA TimeOffset stream.connect
2016-12-01 16:43:46 +08:00
7c59688a12
rtio: simple DMA fixes
2016-12-01 16:30:48 +08:00
46dbc44c8f
rtio: export DMA and CRIInterconnectShared
2016-12-01 16:30:29 +08:00
6c97a97d8c
rtio: support single-master CRI arbiter
2016-12-01 16:30:11 +08:00
a318243083
rtio: CRI arbiter (untested)
2016-12-01 15:41:43 +08:00
cd3f68ba76
rtio: DMA core (untested)
2016-11-30 18:43:19 +08:00
85f2467e2c
rtio: fix RTIO/DRTIO timestamp resolution discrepancy
2016-11-28 15:01:46 +08:00
5460202220
drtio: typo
2016-11-28 14:35:21 +08:00
4e1b497742
drtio: typo
2016-11-28 14:34:58 +08:00
c419c422fa
drtio: support for local RTIO core
2016-11-28 14:33:26 +08:00
1c84d1ee59
Merge branch 'master' into phaser2
...
* master:
rtio: support differential ttl
RELEASE_NOTES: int(a, width=b) removal, use int32/64
pc_rpc: use ProactorEventLoop on Windows (#627 )
2016-11-24 15:05:49 +01:00
95c885b580
rtio: support differential ttl
2016-11-24 15:04:12 +01:00
2d62a89143
rtio: use large data register
2016-11-23 23:23:27 +08:00
9941f3557d
rtio: use only CRI commands for rio/rio_phy resets
2016-11-23 23:19:14 +08:00
347609d765
rtio: auto clear output event data and address
...
This is to support channels where variable length
event data is well-defined through zero-padding.
E.g. in the case of `Spline` zero-padding of events naturally
corresponds to low-order knots.
Use timestamp change as trigger. This assumes that writes to the
timestamp register always precede address and data writes.
It does not break support for ganged writes of the same event
timestamp and data/address to multiple channels or
channel-addresses.
2016-11-23 15:03:36 +01:00
d400c81cb2
rtio: remove debug print
2016-11-23 13:37:14 +08:00
4e931c7dd2
rtio: fix timestamp shift
2016-11-23 13:36:30 +08:00
ffefdb9269
rtio: fix counter readback
2016-11-23 00:54:47 +08:00
aa00627c0e
rtio: fix CRI CSRs
2016-11-22 22:57:04 +08:00
9acc7d135e
gateware: common RTIO interface
2016-11-22 22:46:50 +08:00
3459793586
Merge branch 'master' into drtio
2016-11-22 15:15:22 +08:00
4160490e0a
Merge branch 'phaser' into phaser2
...
* phaser: (23 commits)
RELEASE_NOTES: update
pipistrello: add some inputs
Remove last vestiges of nist_qc1.
Fully drop AD9858 and kc705-nist_qc1 support (closes #576 ).
coredevice.dds: reimplement fully in ARTIQ Python.
compiler: unbreak casts to int32/int64.
analyses.constness: fix false positive on x[...].
inferencer: significantly improve the op-assignment diagnostic.
Fix tests.
Move mu_to_seconds, seconds_to_mu to Core.
artiq_devtool: don't crash on invalid utf-8.
artiq_devtool: detect a race condition during connect.
llvm_ir_generator: handle no-op coercions.
conda: use development version of migen/misoc
Revert accidentally committed code.
Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623 "
analyses.invariant_detection: implement (#622 ).
Fix whitespace.
coredevice.dds: work around the round(numpy.float64()) snafu.
coredevice.dds: update from obsolete int(width=) syntax (fixes #621 ).
...
2016-11-21 17:29:46 +01:00
f7e8961ab0
Merge branch 'master' into phaser
...
* master: (23 commits)
RELEASE_NOTES: update
pipistrello: add some inputs
Remove last vestiges of nist_qc1.
Fully drop AD9858 and kc705-nist_qc1 support (closes #576 ).
coredevice.dds: reimplement fully in ARTIQ Python.
compiler: unbreak casts to int32/int64.
analyses.constness: fix false positive on x[...].
inferencer: significantly improve the op-assignment diagnostic.
Fix tests.
Move mu_to_seconds, seconds_to_mu to Core.
artiq_devtool: don't crash on invalid utf-8.
artiq_devtool: detect a race condition during connect.
llvm_ir_generator: handle no-op coercions.
conda: use development version of migen/misoc
Revert accidentally committed code.
Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623 "
analyses.invariant_detection: implement (#622 ).
Fix whitespace.
coredevice.dds: work around the round(numpy.float64()) snafu.
coredevice.dds: update from obsolete int(width=) syntax (fixes #621 ).
...
2016-11-21 17:29:39 +01:00
whitequark
5e8888d5f3
Fully drop AD9858 and kc705-nist_qc1 support ( closes #576 ).
2016-11-21 15:14:17 +00:00
97a54046e8
rtio: auto clear output event data and address
...
This is to support channels where variable length
event data is well-defined through zero-padding.
E.g. in the case of `Spline` zero-padding of events naturally
corresponds to low-order knots.
Use timestamp change as trigger. This assumes that writes to the
timestamp register always precede address and data writes.
It does not break support for ganged writes of the same event
timestamp and data/address to multiple channels or
channel-addresses.
2016-11-19 16:12:27 +01:00
bcde26f990
Revert "phaser: cap phy data width to 64 temporarily"
...
This reverts commit 342b9e977e
2016-11-18 17:08:44 +01:00
342b9e977e
phaser: cap phy data width to 64 temporarily
2016-11-18 15:46:59 +01:00
d678bb3fb6
phaser: update sawg tests
2016-11-18 15:23:56 +01:00
b9ce2bb1f0
Merge branch 'phaser' into phaser2
...
* phaser: (127 commits)
phaser: use misoc cordic
phaser: fix DDS dummy cfg
runtime: disable the Nagle algorithm entirely.
runtime: buffer RPC send packets.
runtime: don't print debug messages to the UART.
runtime: print microsecond timestamps in debug messages.
artiq_devtool: abort if build failed.
conda: bump llvmlite-artiq dep.
conda: bump llvmlite-artiq dep.
llvm_ir_generator: use !{→unconditionally.}invariant.load metadata.
artiq_devtool: more robust port forwarding.
setup: remove paramiko dependency (optional and developer-only)
artiq_devtool: implement.
artiq_compile: actually disable attribute writeback.
conda: use pythonparser 1.0.
conda: tighten pythonparser dependency (fixes #600 ).
doc: clarify kernel_invariant doc (fixes #609 ).
compiler: Emit all-kernel_invariant objects as LLVM constants
conda: update for LLVM 3.9.
add has_dds, use config flags
...
2016-11-13 17:30:37 +01:00
aedb6747f2
Merge branch 'master' into phaser
...
* master: (47 commits)
runtime: disable the Nagle algorithm entirely.
runtime: buffer RPC send packets.
runtime: don't print debug messages to the UART.
runtime: print microsecond timestamps in debug messages.
artiq_devtool: abort if build failed.
conda: bump llvmlite-artiq dep.
conda: bump llvmlite-artiq dep.
llvm_ir_generator: use !{→unconditionally.}invariant.load metadata.
artiq_devtool: more robust port forwarding.
setup: remove paramiko dependency (optional and developer-only)
artiq_devtool: implement.
artiq_compile: actually disable attribute writeback.
conda: use pythonparser 1.0.
conda: tighten pythonparser dependency (fixes #600 ).
doc: clarify kernel_invariant doc (fixes #609 ).
compiler: Emit all-kernel_invariant objects as LLVM constants
conda: update for LLVM 3.9.
add has_dds, use config flags
Revert "Revert "Revert "Revert "Update for LLVM 3.9.""""
Revert "Revert "Revert "Update for LLVM 3.9."""
...
2016-11-13 16:54:28 +01:00
0c1a76d668
unify rtio/drtio kernel interface
2016-11-01 00:30:16 +08:00
9aa94e1a2d
adapt to migen/misoc changes
2016-10-31 00:53:01 +08:00
ed4d57c638
use new Migen signal attribute API
2016-10-29 21:19:58 +08:00
ea0c304a0c
phaser2: wip
2016-10-27 01:00:42 +02:00
449d1c4dc6
rtio: export CDC modules
2016-10-22 13:03:10 +08:00
f5f7acc1f8
ttl_simple: add pure Input
...
(no Tristate for internal signals)
2016-10-10 17:13:23 +02:00
4a0eaf0f95
phaser: add jesd204b rtio dds
...
gateware: add jesd204b awg
gateware: copy phaser (df3825a)
dsp/tools: update satadd mixin
phaser: no DDS stubs
dsp: accu fix
phaser: cleanup/reduce
sawg: kernel support and docs
sawg: coredevice api fixes
sawg: example ddb/experiment
phaser: add conda package
examples/phaser: typo
sawg: adapt tests, fix accu stb
sawg: tweak dds parameters
sawg: move/adapt/extend tests
sawg: test phy, refactor
phaser: non-rtio spi
phaser: target cli update
phaser: ad9154-fmc-ebz pins
phaser: reorganize fmc signal naming
phaser: add test mode stubs
phaser: txen is LVTTL
phaser: clk spi xfer test
phaser: spi for ad9154 and ad9516
phaser: spi tweaks
ad9154: add register map from ad9144.xml
ad9516: add register map from ad9517.xml and manual adaptation
ad9154_reg: just generate getter/setter macros as well
ad9154: reg WIP
ad9154: check and fix registers
kc705: single ended rtio_external_clk
use single ended user_sma_clk_n instead of p/n to free up one clock sma
kc705: mirror clk200 at user_sma_clock_p
ad9516_regs.h: fix B_COUNTER_MSB
phase: wire up clocking differently
needs patched misoc
kc705: feed rtio_external_clock directly
kc705: remove rtio_external_clk for phaser
phaser: spi tweaks
ad9516: some startup
ad9516_reg fixes
phaser: setup ad9516 for supposed 500 MHz operation
ad9516: use full duplex spi
ad9154_reg: add CONFIG_REG_2
ad9154_reg: fixes
phaser: write some ad9154 config
ad9154_reg: fixes
ad9154: more init, and human readable setup
ad9154/ad9516: merge spi support
ad9154: status readout
Revert "kc705: remove rtio_external_clk for phaser"
This reverts commit d500288bb44f2bf2eeb0c2f237aa207b0a8b1366.
Revert "kc705: feed rtio_external_clock directly"
This reverts commit 8dc7825519e3e75b7d3d29c9abf10fc6e3a8b4c5.
Revert "phase: wire up clocking differently"
This reverts commit ad9cc450ffa35abb54b0842d56f6cf6c53c6fbcc.
Revert "kc705: mirror clk200 at user_sma_clock_p"
This reverts commit 7f0dffdcdd28e648af84725682f82ec6e5642eba.
Revert "kc705: single ended rtio_external_clk"
This reverts commit a9426d983fbf5c1cb768da8f1da26d9b7335e9cf.
ad9516: 2000 MHz clock
phaser: test clock dist
phaser: test freqs
ad9154: iostandards
phaser: drop clock monitor
phaser: no separate i2c
phaser: drive rtio from refclk, wire up sysref
phaser: ttl channel for sync
ad9154: 4x interp, status, tweaks
phaser: sync/sysref 33V banks
phaser: sync/sysref LVDS_25 inputs are VCCO tolerant
phaser: user input-only ttls
phaser: rtio fully from refclk
ad9154: reg name usage fix
ad9154: check register modifications
Revert "ad9154: check register modifications"
This reverts commit 45121d90edf89f7bd8703503f9f317ad050f9564.
ad9154: fix status code
ad9154: addrinc, recal serdes pll
phaser: coredevice, example tweaks
sawg: missing import
sawg: type fixes
ad9514: move setup functions
ad9154: msb first also decreasing addr
phaser: use sys4x for rtio internal ref
phaser: move init code to main
phaser: naming cleanup
phaser: cleanup pins
phaser: move spi to kernel cpu
phaser: kernel support for ad9154 spi
ad9154: add r/w methods
ad9154: need return annotations
ad9154: r/w methods are kernels
ad9154_reg: portable helpers
phaser: cleanup startup kernel
ad9154: status test
ad9154: prbs test
ad9154: move setup, document
phaser: more documentation
2016-10-05 16:17:50 +02:00
a91ed8394c
rtio: add input-only channel
2016-10-05 16:17:50 +02:00
279f0d568d
rtio: support differential ttl
2016-10-05 16:17:50 +02:00
a7dd356d30
rtio/phy/ttl: support 'set sensitivity and sample' command ( #218 )
2016-09-07 15:42:09 +08:00
7a2405146a
rtio: do not reset DDS and SPI PHYs on RTIO reset ( #503 )
2016-07-09 10:07:19 +08:00
900b0cc629
analyzer: make byte_count 64-bit
2016-03-19 19:40:23 +08:00
1bbef94061
analyzer: fix byte_count (again)
2016-03-15 20:49:07 +08:00
85ea70a664
analyzer: fix byte_count
2016-03-15 20:33:08 +08:00
62ac4e3c2e
analyzer: fix EOP generation
2016-03-15 20:25:02 +08:00
b5ec979db3
analyzer: drive wishbone cyc signal
2016-03-15 19:46:12 +08:00
8a6873cab2
analyzer: use EOP, flush pipeline on stop
2016-03-15 17:49:59 +08:00
Florent Kermarrec
8ad799a850
gateware/rtio/analyzer: use new Converter
2016-03-14 15:15:07 +01:00
de718fc819
rtio: fix different address collision detection
2016-03-10 12:15:36 +08:00
f4f95d330b
Merge branch 'master' of github.com:m-labs/artiq
2016-03-10 11:15:30 +08:00
542a375305
rtio: remove NOP suppression capability
...
Back when RTIO was driving TTLs, this functionality made it simpler to use by removing some irrelevant underflows.
The same technique is not applicable to DDS and SPI, so the user will have to deal with such underflows.
This patch makes the behavior of RTIO more consistent and the code simpler.
2016-03-10 09:47:29 +08:00
2e39802a61
rtio/wishbone: make replace configurable
2016-03-10 09:44:05 +08:00
107e5cfbd4
gateware/rtio: factor _BlindTransfer
2016-03-09 19:07:46 +01:00
349a66124b
Merge branch 'master' into rtiobusy
...
* master:
coredevice: fix _DDSGeneric __init__ args
rtio/core: fix syntax
rtio: disable replace on rt2wb channels
examples: dds_bus -> core_dds
fix more multi-DDS-bus problems
runtime: fix dds declarations
support for multiple DDS buses (untested)
2016-03-09 17:58:58 +01:00
3f8e431de6
rtio/core: fix syntax
2016-03-09 17:10:21 +01:00
03b53c3af9
rtio: disable replace on rt2wb channels
2016-03-09 23:37:04 +08:00
2cb58592ff
rtio: add RTIOBusy
2016-03-08 18:04:34 +01:00
2953b069dc
rtio: when rtlink addresses are different, issue collision not replace ( fixes #320 )
2016-03-08 15:58:25 +08:00
71105fd0d7
rtio: collision_error -> collision
2016-03-08 15:38:35 +08:00
a0083f4501
Revert "gateware/rt2wb: only input when active"
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This reverts commit 1b08e65fa1
2016-02-29 16:44:11 +01:00
cb8815cc65
Revert "gateware/rt2wb: support combinatorial ack"
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This reverts commit f73228f248
2016-02-29 16:44:04 +01:00
f73228f248
gateware/rt2wb: support combinatorial ack
2016-02-29 15:40:55 +01:00
1b08e65fa1
gateware/rt2wb: only input when active
2016-02-29 14:56:29 +01:00
f8732acece
rtio.spi: drop unused argument
2016-02-28 21:06:20 +01:00
e7146cc999
gateware.spi: design sketch
2016-02-26 17:03:08 +01:00
68891493a3
analyzer: move common to artiq.protocols
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migen was still pulled in through rtio.__init__.py
2016-01-29 20:26:48 -07:00
cbb60337ae
refactor Analyzer constants to unlink dependencies
2016-01-25 18:03:48 -07:00
080752092c
gateware/rtio: add LogChannel
2015-12-26 22:43:28 +08:00
9ba8dfbf23
gateware/rtio/core: avoid potential python bug
2015-12-26 22:11:57 +08:00
8691f69a3c
gateware/rtio/analyzer: suppress spurious initial reset messages
2015-12-21 18:32:08 +08:00
5769107936
gateware/rtio: keep counter clock domain transfer active during CSR reset
2015-12-20 22:12:34 +08:00
46f59b673f
coredevice: analyzer message decoding
2015-12-20 14:34:16 +08:00
1638f0fa9b
gateware/rtio/analyzer: fix event ordering
2015-12-19 17:04:30 +08:00
64ad38854b
gateware/rtio/analyzer: fix exception message layout
2015-12-18 18:27:06 +08:00
59a3ea4f15
gateware/rtio/analyzer: fix bus write
2015-12-18 15:44:20 +08:00
afaad270cc
rtio/analyzer: fix superficial mistakes
2015-12-16 17:36:36 +08:00
4362f97d67
gateware/rtio/analyzer: complete, untested
2015-12-14 23:53:14 +08:00
