307cd07b9d
suservo: lots of gateware/ runtime changes
...
tested/validated:
* servo enable/disable
* dds interface, timing, io_update, mask_nu
* channel control (en_out, en_iir, profile)
* profile configuration (coefficients, delays, offsets, channel)
* adc timings and waveforms measured
* asf state readback
* adc readback
individual changes below:
suservo: correct rtio readback
suservo: example, device_db [wip]
suservo: change rtio channel layout
suservo: mem ports in rio domain
suservo: sck clocked from rio_phy
suservo: cleanup, straighten out timing
suservo: dds cs polarity
suservo: simplify pipeline
suservo: drop unused eem names
suservo: decouple adc SR from IIR
suservo: expand coredevice layer
suservo: start the correct stage
suservo: actually load ctrl
suservo: refactor/tweak adc timing
suservo: implement cpld and dds init
2018-04-27 13:50:26 +02:00
c83305065a
suservo: add servo/config/status register
2018-04-25 15:59:06 +00:00
fe75064c1e
suservo: cleanup rtio interface
2018-04-24 13:08:40 +00:00
99dd9c7a2a
suservo: fix rtio interface width
2018-04-23 18:30:18 +00:00
934c41b90a
gateware: add suservo
...
from
fe4b60b902
m-labs/artiq#788
2018-04-23 18:24:59 +00:00
f0771765c1
rtio: move CRI write comment to more appropriate location
2018-03-29 23:55:00 +08:00
3a0dfb7fdc
ad53xx: port monitor, moninj dashboard, kc705 target
2018-03-24 16:04:02 +01:00
1553fc8c7d
sed: reset valid
in output sorter
2018-03-23 11:11:11 +00:00
f8c2d54e75
ttl_serdes_ultrascale: configurable SERDES ratio. Also try X4 on Sayma
2018-03-21 13:01:38 +08:00
c8020f6bbd
ttl_serdes_generic: fix/upgrade test
2018-03-20 16:46:57 +08:00
a5825184b7
add ttl_serdes_ultrascale (untested)
2018-03-20 16:07:23 +08:00
fad066f1aa
ttl_serdes_7series: cleanup indentation
...
Inconsistent with other code and confuses text editors.
2018-03-20 15:50:04 +08:00
a315ecd10b
rtio/ttl_serdes_7series: reset IOSERDES ( #958 )
2018-03-14 09:01:29 +08:00
6dfebd54dd
ttl_serdes_7series: use correct IBUFDS_INTERMDISABLE port names
2018-03-12 10:37:33 +08:00
3a6566f949
rtio: judicious spray with reset_less=True
...
Hoping to reduce rst routing difficulty and easier RTIO timing closure.
2018-03-07 14:57:18 +00:00
b0282fa855
spi2: reset configuration in rio_phy
2018-03-07 14:42:11 +00:00
4af7600b2d
Revert "LaneDistributor: try equivalent spread logic"
...
This reverts commit 8b70db5f17
.
Just a shot into the dark.
2018-03-07 11:34:51 +00:00
a6d1b030c1
RTIO: use TS counter in the correct CD
...
artiq/m-labs#938
2018-03-07 11:34:42 +00:00
8b70db5f17
LaneDistributor: try equivalent spread logic
2018-03-07 11:34:42 +00:00
2cbd597416
LaneDistributor: style and signal consolidation [NFC]
2018-03-07 11:34:42 +00:00
50298a6104
ttl_serdes_7series: suppress diff_term in outputs
2018-03-06 14:27:19 +01:00
e356150ac4
ttl_simple: support differential io
2018-03-06 14:27:19 +01:00
c25560baec
sed: more LaneDistributor comments
2018-03-06 20:56:35 +08:00
f40255c968
sed: add comments about key points in LaneDistributor
2018-03-06 20:51:09 +08:00
928d5dc9b3
drtio: raise RTIOLinkError if operation fails due to link lost ( #942 )
2018-03-04 01:02:53 +08:00
cc70578f1f
remove old spi RTIO Phy
2018-03-01 11:19:18 +01:00
f8e6b4f4e3
ad5360: port to spi2
...
* kc705 nist_clock target gateware
* coredevice driver
* moninj code
* test/example/device_db
This is untested as we don't have a AD5360 board right now.
Will be tested with Zotino v1.1
m-labs/artiq#926
2018-02-22 10:25:46 +01:00
37a0d6580b
spi2: add RTIO gateware and coredevice driver
...
1006218997
2018-02-21 13:37:36 +00:00
7a1d71502a
ttl_serdes_7series: drive IBUF and INTERM disables from serdes
2018-02-21 13:37:29 +00:00
476e4fdd56
ttl_serdes_7series: disable IBUF and INTERM when output
2018-02-21 13:37:29 +00:00
ab5f397fea
sed/fifos: use AsyncFIFOBuffered
...
(D)RTIO now passes timing at 150MHz on Kasli.
2018-02-13 20:02:51 +08:00
dc593ec0f0
Merge branch 'rtio-sed' into sed-merge
2018-01-10 12:04:54 +08:00
6d20b71dde
ttl_serdes_7series: refactor IOSERDES
2018-01-02 13:20:47 +01:00
d5b5076f67
gateware/ad5360_monitor: fix SPI data decoding
2017-10-26 11:58:59 +08:00
412548a86c
gateware: add AD5360 monitor (untested)
2017-10-23 20:09:28 +08:00
4fa823b62a
gateware: add support for SPI-over-LVDS
2017-10-23 15:04:01 +08:00
5f083f21a4
rtio/dma: fix signal width
2017-10-08 22:37:46 +08:00
6c049ad40c
rtio: report channel numbers in asynchronous errors
2017-09-29 16:32:57 +08:00
5437f0e3e3
rtio: make sequence errors consistently asychronous
2017-09-29 14:40:06 +08:00
d7ef07a0c2
rtio/sed: document architecture
2017-09-26 16:44:23 +08:00
9905b8723b
rtio/sed: support negative latency compensation
2017-09-26 16:11:08 +08:00
4112e403de
rtio/sed: latency compensation
2017-09-26 15:09:07 +08:00
aa8fc81a87
rtio: allow specifying glbl_fine_ts_width externally
2017-09-23 22:34:55 +08:00
5cf0693758
rtio: use BlindTransfer to report collision and busy errors to sys domain
2017-09-21 22:31:56 +08:00
d74a7d272e
rtio: fix/cleanup parameters
2017-09-21 15:59:48 +08:00
07d3f87c51
rtio/sed: min_space → buffer_space
2017-09-21 14:36:13 +08:00
d8aa75b742
rtio/sed: add minimum buffer space reporting
2017-09-20 11:27:57 +08:00
ddcd6065e8
rtio: drive InputCollector.coarse_timestamp
2017-09-19 17:46:38 +08:00
ff8e17ab89
rtio: use input collector module
2017-09-19 15:53:35 +08:00
4dc80e3d05
rtio: add missing import
2017-09-19 15:53:23 +08:00
d37577a8a1
rtio: add input collector module
2017-09-19 15:30:30 +08:00
6dc9cad2c9
rtio: add explanation about cri.counter
2017-09-19 12:05:12 +08:00
81d6317053
rtio/sed: take global fine TS width
2017-09-18 11:30:49 +08:00
65baca8c57
rtio: clean up error-prone rtlink.get_or_zero()
2017-09-17 16:11:36 +08:00
e2c1d4f3d5
rtio/sed: trigger collision error on non-data replace
2017-09-16 17:01:23 +08:00
0e25154e25
rtio/sed: quash writes to LogChannel
2017-09-16 15:19:30 +08:00
1cfe90b1d9
rtio/sed/Gates: fix fine_ts_width computation
2017-09-16 15:09:21 +08:00
a3bb6c167c
rtio: use SED
2017-09-16 14:13:42 +08:00
131f5e4a3b
rtio/sed/LaneDistributor: fix CRI address
2017-09-16 14:13:01 +08:00
a155a481b1
rtio/sed: add top-level core
2017-09-16 14:04:56 +08:00
92c63ce2e4
rtio/sed: rename fifos/gates, refactor tsc
2017-09-16 14:03:48 +08:00
ac52c7c818
rtio/sed/LaneDistributor: style
2017-09-16 14:02:37 +08:00
6b7a1893c7
rtio/sed/OutputDriver: support channels with different fine timestamp widths
2017-09-16 10:53:30 +08:00
f39ee7ad62
rtio/sed: fix seqn_width
2017-09-16 10:52:37 +08:00
064503f224
rtio/sed/LaneDistributor: support specifying existing CRI
2017-09-16 10:52:13 +08:00
1cb05f3ed5
rtio/sed/LaneDistributor: persist underflow/sequence error until next write
2017-09-16 10:51:44 +08:00
3c922463a0
style
2017-09-15 15:36:46 +08:00
8e5ab90129
rtio/sed: add FIFO wrapper
2017-09-15 15:36:34 +08:00
490c9815a2
rtio/sed: add TSC/gate (untested)
2017-09-14 19:53:21 +08:00
181cb42ba8
rtio/sed: centralize all layouts in one file
2017-09-14 19:52:31 +08:00
1b61442bc3
rtio/sed: fix lane spreading and enable by default
2017-09-13 22:48:10 +08:00
8cfe2ec53a
rtio/sed: fix sequence number width computation
2017-09-13 22:11:41 +08:00
a92a955d1e
rtio/sed: use __all__
2017-09-13 18:17:22 +08:00
c74abccfd5
rtio/sed: lane distributor fixes
2017-09-13 17:50:06 +08:00
bdd96084c5
rtio/sed: add lane distributor (untested)
2017-09-13 00:07:26 +08:00
00ff3f5b0d
rtio/sed: fix output driver busy output
2017-09-11 23:04:52 +08:00
666bc600a2
rtio/sed: add output driver (untested)
2017-09-11 11:10:28 +08:00
1d2ebbe60f
rtio/sed: make ON payload layout configurable, add latency function
2017-09-11 09:06:40 +08:00
c5d6a2ba1a
rtio/sed: more output network fixes
2017-09-10 23:41:04 +08:00
96505a1cd9
rtio/sed: output network fixes
2017-09-10 23:23:10 +08:00
5646e19dc3
rtio/sed: add output network (untested)
2017-09-10 14:38:43 +08:00
Florent Kermarrec
2910b1be5e
artiq/gateware/rtio/dma: replace leave_out with omit in Record.connect
2017-07-04 10:48:06 +02:00
838127d914
rtio: break DMA timing path
2017-07-02 10:24:01 +08:00
911ee4a959
rtio: make pipelined logic reset_less
...
* latency-corrected counters
* registered error logic
2017-06-29 12:55:32 +02:00
f520d4a768
rtio: undo _RelaxedAsyncResetSynchronizer
2017-06-28 22:08:15 +02:00
3cbbcdfe96
sawg: don't enable_replace for Config
...
closes #762
2017-06-28 20:31:40 +02:00
01847271c5
rtio: use reset_less signal for reset fanout
2017-06-28 19:43:55 +02:00
f4c6879c76
sawg: special case Config RTIO address
2017-06-22 10:26:29 +02:00
0d8067256b
rtio: refactor RelaxedAsyncResetSynchronizer
2017-06-18 14:37:08 +02:00
424b2bfbd8
rtio: describe rio and rio_phy domains a bit more
2017-06-17 12:21:07 +02:00
219dfd8984
rtio: add one register level for rio and rio_phy resets
...
* This should give Vivado some wiggle room during PnR.
* It needs three new clock domains which is ugly. But since
AsyncResetSynchronizer can only drive clock domains resets directly
there seems to be no other way to add one register level currently.
2017-06-17 12:17:48 +02:00
2a76034fbc
cri: add note about clearing of o_data
2017-06-16 19:06:00 +02:00
9ab63920e0
Remove Pipistrello support
...
Closes #658
Closes #381
2017-05-15 17:17:44 +08:00
c0100ebc56
rtio: fix indentation
2017-04-06 12:08:13 +08:00
207453efcd
rtio: add a missing case for collision reporting
2017-04-06 11:28:16 +08:00
whitequark
47632f81b1
gateware: CRIArbiter -> CRISwitch.
2017-04-05 16:10:39 +00:00
whitequark
391660e545
gateware: simplify the CRI arbiter to use a plain mux.
2017-04-05 15:09:19 +00:00
12249dac57
rtio: do not clear asynchronous error flags on RTIO reset
2017-04-03 00:20:30 +08:00
db3118b916
drtio: use BlindTransfer for error reporting
2017-04-03 00:18:07 +08:00
b74d6fb9ba
make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads
2017-03-27 16:32:23 +08:00