a7de58b604
rtio: Inout → InOut
2017-03-14 14:18:55 +08:00
d2f2415b50
analyzer: use CRI and connect at RTIO core
...
This causes DMA events to be included in analyzer traces.
2017-03-02 18:47:56 +08:00
f017d1771f
gateware: remove unused configs in targets (not needed with new moninj)
2017-02-25 12:14:56 +08:00
360be0098f
drtio: map local RTIO core on lower channels
2017-02-24 18:15:27 +08:00
b455ea447d
gateware: add moninj to drtio targets
2017-02-21 21:54:47 +08:00
935799dfb7
drtio: fix satellite transceiver clocking
2017-02-04 19:18:35 +08:00
a8ecbd6041
firmware: do not attempt to build Si5324 code when gateware does not support it
2017-02-03 12:27:13 +08:00
d181989de9
drtio: reset Si5324 at each boot
2017-02-03 12:00:58 +08:00
b3697f951a
drtio: forward clocks to SMA connectors for debugging
2017-02-03 12:00:36 +08:00
aafefee7f5
targets: make number of ethmac slots consistent
2017-02-02 23:02:51 +08:00
whitequark
44a9a79f96
firmware: port allocator to Rust.
2017-02-02 10:55:35 +00:00
f512ea42dc
drtio: initialize si5324 in firmware
2017-02-02 18:11:24 +08:00
whitequark
b95db4fa4e
Use four ethmac buffers instead of two.
...
This should address an issue where the host sends a packet burst,
the second packet in a burst gets dropped, the rest also gets
dropped since smoltcp doesn't do reassembly, and the entire dance
is repeated on every retransmit.
2017-01-30 07:42:27 +00:00
9800acea92
drtio: program Si5324 for 150MHz in 3G config
2017-01-30 14:50:12 +08:00
7daab07a29
drtio: fix syntax/import
2017-01-30 13:01:45 +08:00
d8e9949266
drtio: initialize AD9516 clock chip
2017-01-30 11:06:45 +08:00
f6024b6c9a
drtio: fix ad9154 extension registration
2017-01-30 10:59:22 +08:00
43aad0914e
python3.5 -> python3
...
Many things also work with Python 3.6.
2017-01-30 09:24:43 +08:00
94b0783897
drtio: remove support for transceiver SMAs
...
Passive SFP cables do not require bitstream rebuilds and do not cause weird transceiver failures.
2017-01-27 23:33:50 +08:00
whitequark
de17908b38
Revert "Globally update UART baudrate to 921600."
...
This reverts commit b29e2d5bfe
2017-01-25 00:31:28 +00:00
whitequark
b29e2d5bfe
Globally update UART baudrate to 921600.
2017-01-24 22:25:58 +00:00
28a41a2f60
gateware: fix aeb1ba847
2017-01-18 17:11:02 -06:00
ce31ffddb0
firmware: add satellite manager
...
The code duplication with the runtime should be cleaned up later.
2017-01-18 16:50:32 -06:00
b40953800a
gateware: soc -> amp.soc
2017-01-18 15:28:14 -06:00
b8d89d56b1
drtio: add GenericRXSynchronizer
2017-01-15 13:44:43 -06:00
f75fffcf96
drtio: fix satellite RX data corruption
2017-01-10 14:29:30 -06:00
fe53bab953
targets: kc705 -> kc705_dds
2017-01-05 18:40:56 +01:00
082fdaf450
move i2c to libboard, do bit-banging on comms CPU
2017-01-04 21:04:38 +01:00
c08fc8aae9
firmware: support moninj without DDS. Closes #650
2017-01-04 11:26:02 +01:00
455250b3f9
remove DDS_AD9914 and DDS_ONEHOT_SEL
2017-01-03 22:04:25 +01:00
7ff77bceac
move AD9616 and AD9154 initialization to firmware
2017-01-03 16:11:38 +01:00
417708af90
phaser: add note about DDS defines ( #650 )
2017-01-02 22:15:21 +01:00
61abd994e9
Revert "fir: force dsp48"
...
This reverts commit 0ad433832d1b6dcd803ffa086ae73b2ee0568326.
2016-12-14 19:16:07 +01:00
641d109786
fir: force dsp48
2016-12-14 19:16:07 +01:00
527757b471
kc705_drtio: use ad9154_fmc_ebz
2016-12-13 14:30:26 +08:00
03d13d3811
phaser: dma/drtio changes
2016-12-12 17:46:36 +01:00
c63fa46430
Merge branch 'phaser2'
...
* phaser2: (157 commits)
sawg/hbf: tweak pipeline for timing
fir: register multiplier output
conda/phaser: build-depend on numpy
sawg: reduce coefficient width
sawg: fix latency
test/fir: needs mpl. don't run by default
test/sawg: patch spline
sawg: use ParallelHBFCascade to AA [WIP]
fir: add ParallelHBFCascade
fir: add ParallelFIR and test
gateware/dsp: add FIR and test
README_PHASER: update
sawg: documentation
sawg: extract spline
sawg: document
sawg: demo_2tone
sawg: round to int64
gateware/phaser -> gateware/ad9154_fmc_ebz
phaser: fix typo
sawg: merge set/set64
...
2016-12-12 17:31:39 +01:00
0a9f69a3ed
kc705_drtio_master: add missing rtio_core CSRs
2016-12-09 19:23:36 +08:00
bc36bda94a
perform RTIO init on comms CPU side
2016-12-09 14:16:55 +08:00
b311830fc4
kc705: fix drtio_aux address conflict
2016-12-06 18:28:48 +08:00
4669d3f02f
kc705_drtio_satellite: add MiSoC system, hook up auxiliary controller
2016-12-06 14:56:42 +08:00
f4b7d39a69
kc705_drtio_master: hook up auxiliary controller
2016-12-06 14:56:15 +08:00
5d145ff912
drtio: add false paths between sys and transceiver clocks
2016-12-03 23:03:01 +08:00
4b97b9f8ce
drtio: add clock constraints
2016-12-03 22:17:29 +08:00
cbf1004df3
gateware/phaser -> gateware/ad9154_fmc_ebz
2016-12-02 14:11:41 +01:00
6353f6d590
drtio: support different configurations and speeds
2016-12-02 17:22:22 +08:00
d4cb1eb998
kc705: integrate DMA
2016-12-01 16:31:00 +08:00
27160f5912
phaser: make sysref input only for timing
2016-11-29 15:28:10 +01:00
cf342eca6e
kc705_drtio_master: fix number of fine RTIO timestamp bits
2016-11-29 10:44:27 +08:00
f4c6d6eb69
kc705_drtio_master: fix number of fine RTIO timestamp bits
2016-11-28 15:18:54 +08:00
85f2467e2c
rtio: fix RTIO/DRTIO timestamp resolution discrepancy
2016-11-28 15:01:46 +08:00
9fdd29ddae
drtio: connect KernelInitiator correctly
2016-11-28 14:36:18 +08:00
c419c422fa
drtio: support for local RTIO core
2016-11-28 14:33:26 +08:00
55e37b41ec
phaser: use ttl_simple.Input for sync
2016-11-24 15:55:26 +01:00
8060652913
phaser: use Inout_8X
2016-11-24 15:21:03 +01:00
617650f3b2
phaser: extract target
2016-11-24 15:20:51 +01:00
32fdacd95a
Merge remote-tracking branch 'm-labs/master' into phaser2
...
* m-labs/master:
runtime: don't attempt to perform writeback if disabled in kernel.
runtime: print trace level log messages to UART during startup.
runtime: support for targets without RTIO log channel
runtime: support for targets without I2C
kc705: remove stale DDS definition
runtime: show a prompt to erase startup/idle kernels.
2016-11-23 14:56:29 +01:00
0443f83d5e
runtime: support for targets without RTIO log channel
2016-11-23 10:50:55 +08:00
0c49679984
runtime: support for targets without RTIO log channel
2016-11-23 10:48:26 +08:00
fbd83cf9ee
kc705: remove stale DDS definition
2016-11-22 22:48:22 +08:00
9acc7d135e
gateware: common RTIO interface
2016-11-22 22:46:50 +08:00
0aaf120ca7
kc705: remove stale DDS definition
2016-11-22 22:46:19 +08:00
3459793586
Merge branch 'master' into drtio
2016-11-22 15:15:22 +08:00
4160490e0a
Merge branch 'phaser' into phaser2
...
* phaser: (23 commits)
RELEASE_NOTES: update
pipistrello: add some inputs
Remove last vestiges of nist_qc1.
Fully drop AD9858 and kc705-nist_qc1 support (closes #576 ).
coredevice.dds: reimplement fully in ARTIQ Python.
compiler: unbreak casts to int32/int64.
analyses.constness: fix false positive on x[...].
inferencer: significantly improve the op-assignment diagnostic.
Fix tests.
Move mu_to_seconds, seconds_to_mu to Core.
artiq_devtool: don't crash on invalid utf-8.
artiq_devtool: detect a race condition during connect.
llvm_ir_generator: handle no-op coercions.
conda: use development version of migen/misoc
Revert accidentally committed code.
Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623 "
analyses.invariant_detection: implement (#622 ).
Fix whitespace.
coredevice.dds: work around the round(numpy.float64()) snafu.
coredevice.dds: update from obsolete int(width=) syntax (fixes #621 ).
...
2016-11-21 17:29:46 +01:00
f7e8961ab0
Merge branch 'master' into phaser
...
* master: (23 commits)
RELEASE_NOTES: update
pipistrello: add some inputs
Remove last vestiges of nist_qc1.
Fully drop AD9858 and kc705-nist_qc1 support (closes #576 ).
coredevice.dds: reimplement fully in ARTIQ Python.
compiler: unbreak casts to int32/int64.
analyses.constness: fix false positive on x[...].
inferencer: significantly improve the op-assignment diagnostic.
Fix tests.
Move mu_to_seconds, seconds_to_mu to Core.
artiq_devtool: don't crash on invalid utf-8.
artiq_devtool: detect a race condition during connect.
llvm_ir_generator: handle no-op coercions.
conda: use development version of migen/misoc
Revert accidentally committed code.
Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623 "
analyses.invariant_detection: implement (#622 ).
Fix whitespace.
coredevice.dds: work around the round(numpy.float64()) snafu.
coredevice.dds: update from obsolete int(width=) syntax (fixes #621 ).
...
2016-11-21 17:29:39 +01:00
93c310dfa5
pipistrello: add some inputs
2016-11-21 23:43:41 +08:00
whitequark
6aa5d9f6c6
Remove last vestiges of nist_qc1.
2016-11-21 15:36:22 +00:00
whitequark
5e8888d5f3
Fully drop AD9858 and kc705-nist_qc1 support ( closes #576 ).
2016-11-21 15:14:17 +00:00
whitequark
f4b7666768
coredevice.dds: reimplement fully in ARTIQ Python.
...
This commit also drops AD9858 support from software.
2016-11-21 15:13:26 +00:00
174c4be218
phaser: false paths sys<->{jesd,phy.tx}
2016-11-21 09:57:33 +01:00
ad1049d59a
Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623 "
...
This reverts commit 4a62e09bd4
2016-11-20 21:35:07 +08:00
whitequark
30598720f4
Fix whitespace.
2016-11-20 09:50:00 +00:00
David Leibrandt
4a62e09bd4
gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623
2016-11-20 15:22:32 +08:00
b714137f76
phaser: 150 MHz rtio/jesd clock
2016-11-19 13:16:30 +01:00
2e482505c6
phaser: fix DDS dummy cfg
2016-11-13 17:08:59 +01:00
aedb6747f2
Merge branch 'master' into phaser
...
* master: (47 commits)
runtime: disable the Nagle algorithm entirely.
runtime: buffer RPC send packets.
runtime: don't print debug messages to the UART.
runtime: print microsecond timestamps in debug messages.
artiq_devtool: abort if build failed.
conda: bump llvmlite-artiq dep.
conda: bump llvmlite-artiq dep.
llvm_ir_generator: use !{→unconditionally.}invariant.load metadata.
artiq_devtool: more robust port forwarding.
setup: remove paramiko dependency (optional and developer-only)
artiq_devtool: implement.
artiq_compile: actually disable attribute writeback.
conda: use pythonparser 1.0.
conda: tighten pythonparser dependency (fixes #600 ).
doc: clarify kernel_invariant doc (fixes #609 ).
compiler: Emit all-kernel_invariant objects as LLVM constants
conda: update for LLVM 3.9.
add has_dds, use config flags
Revert "Revert "Revert "Revert "Update for LLVM 3.9.""""
Revert "Revert "Revert "Update for LLVM 3.9."""
...
2016-11-13 16:54:28 +01:00
99ad9b5917
add has_dds, use config flags
2016-11-08 23:33:03 +08:00
d158c69be0
phaser: fix frequency comment
2016-11-05 16:54:23 +01:00
47b9868c68
kc705_drtio_master: pretend drtio is rtio
2016-11-05 23:48:29 +08:00
de065b7578
kc705_drtio_satellite: set output dir
2016-11-05 23:48:15 +08:00
whitequark
00100148f1
Si5324: actually write value of N32 into registers.
2016-11-02 07:09:04 +00:00
1ed3278783
remove stale TODO
2016-11-02 10:53:54 +08:00
whitequark
a6ae254796
Si5324: update to free run from XA/XB, with CKIN1 having priority.
2016-11-01 16:01:24 +00:00
07ad00c1ca
drtio: split kernel/system CSRs
2016-10-31 18:09:36 +08:00
9aa94e1a2d
adapt to migen/misoc changes
2016-10-31 00:53:01 +08:00
2392113bb6
kc705: use misoc clock for false path
2016-10-30 11:16:04 +08:00
c656a53532
kc705: clean up clock constraints
2016-10-29 21:28:01 +08:00
ed4d57c638
use new Migen signal attribute API
2016-10-29 21:19:58 +08:00
da5208e160
drtio: add master gateware target
2016-10-29 17:31:15 +08:00
2a1e529dcf
phaser: DDS config dummies
2016-10-28 01:58:08 +02:00
c428800caf
phaser: spi, sma_gpio: 2.5 V
2016-10-27 15:53:49 +02:00
e7dbed3b02
gateware: KC705 satellite target
2016-10-17 19:23:45 +08:00
Florent Kermarrec
0259c80015
phaser/kc705: remove transceiver initialization workaround
2016-10-14 19:06:43 +02:00
b41b9de905
phaser: tag jesd as clock net
2016-10-14 10:46:33 +02:00
4ea3dea217
phaser: broad spectrum antibiotics with xilinx false paths
2016-10-14 10:22:03 +02:00
e400f8d672
phaser: add two more registers before jesd
2016-10-14 09:54:56 +02:00
3c9c42c779
phaser: drive rtio from jesd-bufg
2016-10-14 02:26:19 +02:00
808874a523
phaser: drive cd_jesd with BUFG
2016-10-14 01:57:48 +02:00
342d6d756e
phaser: bypass gtx phalign
2016-10-14 00:59:53 +02:00
89150c9817
phaser: 10G line rate
2016-10-14 00:53:38 +02:00
