Commit Graph

6454 Commits

Author SHA1 Message Date
ciciwu
9a96387dfe
phaser: fix docstring formatting (#1866) 2022-03-08 19:03:30 +08:00
b02abc2bf4 remove legacy versioning files 2022-03-06 18:30:08 +08:00
ac55da81d8 core: support precompilation of kernels 2022-03-06 18:25:18 +08:00
232f28c0e8 kern_hw: fix return type 2022-03-04 15:16:14 +08:00
51fa1b5e5e drtio: fix i2c switch 2022-03-04 15:16:14 +08:00
17ecd35530 test_i2c: fix for missing readback 2022-03-01 17:40:20 +08:00
a85b4d5f5e
I2C API for PCA9547 support (#1860) 2022-03-01 15:07:53 +08:00
338bb189b4 dashboard: fix typo (#1858) 2022-02-26 08:58:03 +08:00
Leon Riesebos
c4292770f8
Kasli JSON description for SPI over DIO cards (#1800) 2022-02-26 07:36:00 +08:00
2b918ac6f7 coredevice: merge pcf8574a into i2c 2022-02-25 19:01:14 +08:00
1b80746f48 Remove outer_final
We don't need to know whether there's a outer finally block
that's already implicit in the current break and continue
target.

Signed-off-by: Michael Birtwell <michael.birtwell@oxionics.com>
2022-02-24 19:58:33 +08:00
2d6215158f Fix try/finally:while:try compilation
When we have a trys inside a loop then we want to make sure any
finallys are executed by break and continue inside this try. But
this shouldn't pull finallys defined outside the loop in to the
loop. This change resets the `outer_final` attribute when
visiting for and while loops so that this doesn't happen.

Signed-off-by: Michael Birtwell <michael.birtwell@oxionics.com>
2022-02-24 19:58:33 +08:00
0da7b83176 runtime: add nac3 exception symbols 2022-02-23 11:04:53 +08:00
Steve Fan
ad656d1e53
dashboard: add device database reload action in context menu (#1853) 2022-02-22 16:18:27 +08:00
Mike Birtwell
a106ed0295
artiq_flash: don't try to make rtm_binary_dir if binary_dir unset (#1851)
Signed-off-by: Michael Birtwell <michael.birtwell@oxionics.com>
2022-02-18 18:54:17 +08:00
c8b9eed9c9 fastino: add comments about sideeffects on v0.1 2022-02-16 14:42:22 +00:00
08b65470cd fastino: robustify init()
* init() now also clear and resets more state including the interpolators.
  If not done, this PLL unlocks/locks may lead to random interpolator state
  on boot to which the CICs react badly.
* Use and expose `t_frame`
* Clarify implementation state of `read()`
2022-02-16 14:34:22 +00:00
65eab31f23 simplify board package format and artiq_flash 2022-02-14 15:54:17 +08:00
b893d97d7b afws_client: add login successful message 2022-02-08 21:52:48 +08:00
b6f5ba8b5b afws_client: improve error message when output already exists 2022-02-08 21:26:12 +08:00
cc69482dad afws: nix requires full Git commit hash 2022-02-08 21:05:39 +08:00
833acb6925 add AFWS client 2022-02-07 14:28:00 +08:00
d5eec652ee tester: specify att with dB 2022-02-07 14:22:52 +08:00
a74196aa27 mirny: allow set attenuation with dB 2022-02-07 14:22:52 +08:00
Steve Fan
798a412c6f
comm_moninj: set keepalive for socket (#1843) 2022-02-04 13:51:19 +08:00
David Nadlinger
e45cb217be firmware: Explicitly use wrapping integer math in PRNGs
Patch by Hannah McLaughlin; apparently, the overflow actually
doesn't get checked/reported without `opt-level = 2` and
`lto = "thin"`.
2022-02-03 23:57:17 +00:00
ef25640937 compiler: fix noreturn attribute on __artiq_resume 2022-02-01 19:01:40 +08:00
Steve Fan
34008b7a21
Backport of "fixes alignment and size problem" from artiq-zynq (#1841) 2022-01-28 20:49:55 +08:00
93328ad8ee compiler: only allow constant exception messages
Otherwise, the exception message might be allocated on a stack, and will
become a dangling pointer when the exception is raised.
This will break some code that constructs exceptions with a function by
passing the message as a parameter because we cannot know if the parameter
is a constant. A way to mitigate this would be to defer this check to
LLVM IR codegen stage, and do inlining first for those exception
allocation functions, but I am not sure if we will guarantee inlining
for certain functions, and whether this is really needed.
2022-01-28 09:01:39 +08:00
Steve Fan
234a82aaa9
dashboard: prioritize min as part of default value resolution (#1839) 2022-01-27 17:45:09 +08:00
ee511758ce fix typo 2022-01-26 07:51:35 +08:00
9d43762695 test: fixed lit tests
Note that because we changed exception representation from using string
names as exception identifier into using integer IDs, we need to
initialize the embedding map in order to allocate the integer IDs. Also,
we can no longer print the exception names and messages from the kernel,
we will need the host to map exception IDs to names, and may need the
host to map string IDs to actual strings (messages can be static strings
in the firmware, or strings stored in the host only).

We now check for exception IDs for lit tests, which are fixed because we
preallocated all builtin exceptions.
2022-01-26 07:16:54 +08:00
4132c450a5 firmware: runtime changes for exception
Ported from:
M-Labs/artiq-zynq#162

This includes new API for exception handling, some refactoring to avoid
code duplication for exception structures, and modified protocols to
send nested exceptions and avoid string allocation.
2022-01-26 07:16:54 +08:00
536b3e0c26 test: added test case for nested exceptions and try 2022-01-26 07:16:54 +08:00
ba34700798 coredevice: report nested exceptions 2022-01-26 07:16:54 +08:00
6ec003c1c9 compiler: fixed dead code eliminator
Instead of removing basic blocks with no predecessor, we will now mark
and remove all blocks that are unreachable from the entry block. This
can handle loops that are dead code. This is needed as we will now
generate more complicated code for exception handling which the old dead
code eliminator failed to handle.
2022-01-26 07:16:54 +08:00
da4ff44377 compiler: fixed try codegen and allocate exceptions
Exceptions are now allocated in the runtime when we raise the exception,
and destroyed when we exit the catch block. Nested exception and try
block is now supported, and should behave the same as in CPython.
Exceptions raised in except blocks will now unwind through finally
blocks, matching the behavior in CPython. Reraise will now preserve
backtrace.

Phi block LLVM IR generation is modified to handle landingpads, which
one ARTIQ IR will map to multiple LLVM IR.
2022-01-26 07:16:54 +08:00
4644e105b1 compiler: modified exception representation
Exception name is replaced by exception ID, which requires no
allocation. Other strings in the exception can now be 'host-only'
strings, which is represented by a CSlice with len = usize::MAX and
ptr = key, to avoid the need for allocation when raising exceptions
through RPC.
2022-01-26 07:16:54 +08:00
hartytp
715bff3ebf
Revert "Merge pull request #1544 from airwoodix/dataset-compression" (#1838)
* Revert "Merge pull request #1544 from airwoodix/dataset-compression"

This reverts commit 311a818a49, reversing
changes made to 7ffe4dc2e3.

* fix accidental revert of f42bea06a8
2022-01-25 10:02:15 +08:00
Steve Fan
3f812c4c2c
comm_kernel: fix RPC exception handling (#1801) 2022-01-12 15:23:37 +08:00
Steve Fan
de5892a00a
comm_kernel: check if elements are within bounds for RPC list (#1824) 2022-01-11 17:16:45 +08:00
Peter Drmota
4eee49f889 gateware.test.suservo: Fix tests for python >=3.7
Closes #1748
2022-01-11 17:16:09 +08:00
9eee0e5a7b gateware/suservo: fix profile no. in test
Follow-up/Test update for 9d49302.
2022-01-11 14:20:47 +08:00
d7dd75e833 comm_kernel: fix off-by-one error for numeric value range check 2022-01-11 10:13:42 +08:00
095fb9e333
add Almazny support (#1780) 2022-01-11 09:55:39 +08:00
4e3e0d129c firmware: fix compilation warning 2022-01-11 09:31:26 +08:00
12ee326fb4 firmware: fixed personality function 2022-01-11 09:30:19 +08:00
61349f9685 sinara_tester: fix outdated API 2022-01-10 17:23:28 +08:00
cea0a15e1e suservo: use default urukul profile 2022-01-10 16:21:39 +08:00
8b45f917d1 urukul: use default profile 2022-01-10 16:21:39 +08:00
6542b65db3 compiler: fixed exception codegen issues 2022-01-10 15:54:29 +08:00
9f90088fa6 compiler: generate appropriate landingpad IR
When used together with modified personality function, we got ~20%
performance improvement in exception unwinding with zynq.
2022-01-10 15:54:29 +08:00
5e1847e7c1 compiler: rename variables to retainedNodes
Part of the changes that was made to LLVM 6 by the time that LLVM 7 was released.
LLVM commit: 2c864551df
LLVM differential review: https://reviews.llvm.org/D45024
2022-01-10 11:28:37 +08:00
6f3c49528d compiler: revert cabe5ac
The lack of debug emitter causes #1821.
2022-01-10 11:26:03 +08:00
eaa1505c94 update documentation (#1820) 2022-01-08 11:55:52 +08:00
Leon Riesebos
f42bea06a8 worker_db: removed warning for writing a dataset that is also in the archive
Signed-off-by: Leon Riesebos <leon.riesebos@duke.edu>
2022-01-08 11:48:18 +08:00
9d493028e5 gateware/suservo: write to profile 7
Fixes #1817.
2022-01-07 16:41:19 +08:00
bbac477092 tools: fix importlib issue 2021-12-21 13:20:11 +08:00
c0a7be0a90 llvm_ir: move stacksave before lltag alloca in build_rpc
Signed-off-by: Steve Fan <sf@m-labs.hk>
2021-12-19 00:07:07 +00:00
9e5e234af3 stop using explicit ProactorEventLoop on Windows
It is now the default in Python.
2021-12-14 20:06:38 +08:00
352317df11 test_dataset_db: remove (too much breakage on Windows) 2021-12-14 19:27:15 +08:00
a518963a47 test_dataset_db: disable tests broken on windows 2021-12-14 19:19:22 +08:00
37f14d94d0 test_dataset_db: fix for windows 2021-12-14 19:07:17 +08:00
Peter Drmota
7c664142a5
Simplified use of the AD9910 RAM feature (#1584)
* coredevice: Change Urukul default single-tone profile to 7

This allows using the internal profile control in RAM modulation mode (which always starts to play back at profile 0) without competing for the content of the profile 0 register used in single tone mode.

Signed-off-by: Peter Drmota <peter.drmota@physics.ox.ac.uk>

* ad9910/set_mu: comment on caveats when setting register

* ad9910: avoid unnecessary write/param

Credit: Solution proposed by @pmldrmota in https://github.com/m-labs/artiq/pull/1584#issuecomment-987774353

* revert 1064fdff (`set_mu()` comments)

158a7be7 had addressed this issue.

Co-authored-by: occheung <dc@m-labs.hk>
2021-12-13 23:44:03 +08:00
33a9ca2684 tools/file_import: use SourceFileLoader
This allows loading modules from files with extensions not in
importlib.machinery.SOURCE_SUFFIXES

Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-12-09 11:47:04 +08:00
1def0d98c5
Merge branch 'master' into dataset-compression 2021-12-06 12:40:30 +08:00
Leon Riesebos
7ffe4dc2e3 coredevice: set default pow for ad9912 set_mu() 2021-12-06 12:34:55 +08:00
Leon Riesebos
9e3ea4e8ef coredevice: fixed type annotations for AD9910 2021-12-06 12:34:55 +08:00
Steve Fan
4a6bea479a
Host report for async error upon kernel termination (#1791)
Closes #1644
2021-12-04 13:33:24 +08:00
7953f3d705 kc705: add drtio 100mhz clk switch 2021-12-03 17:19:11 +08:00
f281112779 satman: add 100mhz si5324 settings
siphaser: add calculated vco for 100mhz comment
2021-12-03 17:19:11 +08:00
eec3ea6589 siphaser: add support for 100mhz rtio 2021-12-03 17:19:11 +08:00
Etienne Wodey
9f830b86c0
kasli: add SED lanes count option to HW description JSON file (#1745)
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
2021-12-03 17:05:35 +08:00
b8e7add785 language: remove deprecated set_dataset(..., save=...) 2021-12-01 22:41:34 +08:00
David Nadlinger
c6039479e4 compiler: Add lit test for call site attributes [nfc] 2021-11-27 04:46:07 +00:00
David Nadlinger
63b5727a0c compiler: Also emit byval argument attributes at call sites
See previous commit.

GitHub: Fixes #1599.
2021-11-27 04:45:50 +00:00
David Nadlinger
9b01db3d11 compiler: Emit sret call site argument attributes
LLVM 6 seemed not to mind the mismatch, but more recent
versions produce miscompilations without this.

Needs llvmlite support (GitHub: numba/llvmlite#702).
2021-11-27 04:44:41 +00:00
6a433b2fce artiq_sinara_tester: test Urukul attenuator digital control 2021-11-24 18:57:16 +08:00
9423428bb0 drtio: fix crc32 offset address 2021-11-24 12:00:56 +08:00
b49f813b17 artiq_flash: ignore checking non-RTM artifacts if unused 2021-11-18 16:59:32 +08:00
Peter Drmota
20e079a381
AD9910 driver feature extension and SUServo IIR readability (#1500)
* coredevice.ad9910: Add set_cfr2 function and extend arguments of set_cfr1 and set_sync

* SUServo: Wrap CPLD and DDS devices in a list

* SUServo: Refactor [nfc]

Co-authored-by: drmota <peter.drmota@physics.ox.ac.uk>
Co-authored-by: David Nadlinger <code@klickverbot.at>
2021-11-15 12:09:16 +08:00
db3e5e83e6 bump misoc 2021-11-08 16:59:08 +08:00
09945ecc4d gateware: fix drtio/dma tests 2021-11-08 16:59:08 +08:00
02119282b8 build_soc: build VexRiscv_G if not kasli v1.x 2021-11-08 16:59:08 +08:00
750b0ce46d ddb_temp: select appropriate compiler target 2021-11-08 16:59:08 +08:00
531670d6c5 dyld: check ABI 2021-11-08 16:59:08 +08:00
0f660735bf ll_gen: adjust csr address by detecting target class 2021-11-08 16:59:08 +08:00
0755757601 compiler/tb: use FPU 2021-11-08 16:59:08 +08:00
0d708cd61a compiler/target: split RISCV target into float/non-float 2021-11-08 16:59:08 +08:00
03b803e764 firmware: adjust csr separation 2021-11-08 16:59:08 +08:00
b3e315e24a rust: find json file using CARGO_TRIPLE 2021-11-08 16:59:08 +08:00
0898e101e2 board_misoc: reuse riscv dir for comm & kernel 2021-11-08 16:59:08 +08:00
cb247f235f gateware: pass adr_w/data_w to submodules 2021-11-08 16:59:08 +08:00
90f944481c kernel_cpu: add fpu if not kasli v1.x 2021-11-08 16:59:08 +08:00
d84ad0095b comm_cpu: select 64b bus if not kasli v1.x 2021-11-08 16:59:08 +08:00
dd68b4ab82 mailbox: parametrize address width 2021-11-08 16:59:08 +08:00
c6e0e26440 drtio: accept 32b/64b bus 2021-11-08 16:59:08 +08:00
8da924ec0f dma: set conversion granularity using bus width 2021-11-08 16:59:08 +08:00
591507a7c0
Merge pull request #1774 from m-labs/fastino-cic
Fastino cic
2021-10-28 17:44:20 +02:00
5a5b0cc7c0 fastino: expand docs 2021-10-28 15:19:48 +00:00