490c9815a2
rtio/sed: add TSC/gate (untested)
2017-09-14 19:53:21 +08:00
181cb42ba8
rtio/sed: centralize all layouts in one file
2017-09-14 19:52:31 +08:00
1b61442bc3
rtio/sed: fix lane spreading and enable by default
2017-09-13 22:48:10 +08:00
8cfe2ec53a
rtio/sed: fix sequence number width computation
2017-09-13 22:11:41 +08:00
a92a955d1e
rtio/sed: use __all__
2017-09-13 18:17:22 +08:00
feec6298a5
rtio/sed: add lane distributor simulation unittest
2017-09-13 18:00:16 +08:00
c74abccfd5
rtio/sed: lane distributor fixes
2017-09-13 17:50:06 +08:00
bdd96084c5
rtio/sed: add lane distributor (untested)
2017-09-13 00:07:26 +08:00
faf54127ac
rtio/sed: remove VCD fine in unittest
2017-09-11 23:07:09 +08:00
a2b7894134
rtio/sed: add output driver simulation unittest
2017-09-11 23:05:10 +08:00
00ff3f5b0d
rtio/sed: fix output driver busy output
2017-09-11 23:04:52 +08:00
64d9381c36
rtio/sed: remove uneeded yield in test_sed_output_network
2017-09-11 23:02:56 +08:00
666bc600a2
rtio/sed: add output driver (untested)
2017-09-11 11:10:28 +08:00
1d2ebbe60f
rtio/sed: make ON payload layout configurable, add latency function
2017-09-11 09:06:40 +08:00
527b403bb1
rtio/sed: add output network simulation unittest
2017-09-10 23:41:20 +08:00
c5d6a2ba1a
rtio/sed: more output network fixes
2017-09-10 23:41:04 +08:00
96505a1cd9
rtio/sed: output network fixes
2017-09-10 23:23:10 +08:00
5646e19dc3
rtio/sed: add output network (untested)
2017-09-10 14:38:43 +08:00
1dab7df846
kc705_sma_spi: fix permissions
2017-08-20 10:54:24 -04:00
df4f38a1e4
kc705: add pullup on SD card MISO
2017-07-24 22:26:16 +08:00
a201a9abd9
drtio: multilink transceiver interface
2017-07-18 13:27:33 +08:00
9045b4cc19
drtio: initial firmware support for multi-link
2017-07-18 00:40:21 +08:00
4deb5f6a45
gateware: use new MiSoC Wishbone address system
2017-07-13 19:16:49 +08:00
mntng
40ca951750
kc705: add SPI bus for memory card
...
This will be useful for SPI unit tests using a SD card as victim.
2017-07-12 00:27:44 +08:00
7b130a2c32
sawg: confirm smooth(order=3)
2017-07-07 11:36:03 +02:00
2f1029c292
Revert "sawg: advance dds 1/2 by one sample group"
...
This reverts commit 8e0a1cbdc8#772
The underlying issue is still the same. You will always find something that does not match when trying to compare the DDS with the parallelized DUC. They are just different. I could correct it for phase but then it will fail for amplitude. Or you'll compare the offset channel to phase1 or amplitude1. Let's state that equal things are well synchronized but unequal things may have a deterministic latency difference of strictly less than one coarse RTIO cycle.
2017-07-04 17:55:19 +02:00
8e0a1cbdc8
sawg: advance dds 1/2 by one sample group
...
closes #772
2017-07-04 16:51:58 +02:00
91ca9fbcad
sawg: also give offset some headroom
...
closes #771
2017-07-04 16:50:06 +02:00
78d1f0fdf6
sawg: fix PhasedAccu resets
2017-07-04 11:56:21 +02:00
Florent Kermarrec
2910b1be5e
artiq/gateware/rtio/dma: replace leave_out with omit in Record.connect
2017-07-04 10:48:06 +02:00
838127d914
rtio: break DMA timing path
2017-07-02 10:24:01 +08:00
911ee4a959
rtio: make pipelined logic reset_less
...
* latency-corrected counters
* registered error logic
2017-06-29 12:55:32 +02:00
600a48ac61
dsp.fir: cleanup
2017-06-29 12:18:48 +02:00
dca662a743
dsp.fir: pipeline final systolic adder
2017-06-29 11:33:19 +02:00
32a33500c8
dsp.fir: actively cull zero delays
2017-06-29 11:24:56 +02:00
f520d4a768
rtio: undo _RelaxedAsyncResetSynchronizer
2017-06-28 22:08:15 +02:00
3cbbcdfe96
sawg: don't enable_replace for Config
...
closes #762
2017-06-28 20:31:40 +02:00
f2632e0fd1
sawg: adapt latency to fir changes
...
closes #748
2017-06-28 20:12:30 +02:00
e7db2c6578
dsp.accu: reset_less outputs
2017-06-28 20:04:58 +02:00
6bb994228f
dsp.fir: drop x shift
2017-06-28 19:55:15 +02:00
01847271c5
rtio: use reset_less signal for reset fanout
2017-06-28 19:43:55 +02:00
b9859cc0c3
dsp.fir: remove old/wrong comment
2017-06-28 19:21:57 +02:00
55b5b87490
fir: simplify latency compensation
...
Don't try to tweak out the last bit of latency by feeding the HBF input
early. Instead feed it late so the interpolated samples are early and
the latency is an even multiple of the super-sample cycle.
2017-06-28 19:13:43 +02:00
d1e5dd334f
sawg: use pipeline reset
2017-06-28 19:09:39 +02:00
6418205906
dsp.fir: use pipelin-reset
2017-06-28 19:09:21 +02:00
07f5e99140
dsp/sat_add: works after previous changes
2017-06-22 18:24:22 +02:00
f78d5a87e9
dsp/test: skip and fix sat_add
2017-06-22 18:01:31 +02:00
47928a2c0d
sawg: disable limiter
...
temporary workaround to permit testing other aspects
2017-06-22 17:31:04 +02:00
cd2ac53bc5
dsp/sat_add: make width mandatory
2017-06-22 17:28:39 +02:00
9b940aa876
dsp/sat_add: spell out logic more
2017-06-22 16:55:13 +02:00
