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Code Pull Requests Activity
7,735 Commits 14 Branches 35 Tags 23 MiB
Commit Graph

49 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq ea95d91428 wrpll: separate collector reset 2020-11-09 17:57:13 +08:00
Sebastien Bourdeauducq d185f1ac67 wrpll: fix mulshift (2) 2020-10-17 00:32:02 +08:00
Sebastien Bourdeauducq 3f076bf79b wrpll: fix mulshift 2020-10-16 22:05:37 +08:00
Sebastien Bourdeauducq db62cf2abe wrpll: convert tests to self-checking unittests 2020-10-08 18:38:01 +08:00
Sebastien Bourdeauducq 07d43b6e5f wrpll: babysit Vivado DSP retiming 
Design now passes timing.
 2020-10-08 17:51:27 +08:00
Sebastien Bourdeauducq 6248970ef8 wrpll: clean up matlab comparison test 2020-10-08 15:40:15 +08:00
hartytp cd8c2ce713 wrpll: add test to compare collector+filter against Matlab simulation 2020-10-08 15:36:56 +08:00
hartytp d780faf4ac wrpll.si549: initialize the clock divider to a sensible value 2020-10-08 15:32:27 +08:00
hartytp 7d7be6e711 wrpll.core: move collector into helper CD so we can get tags out while the filters are reset 2020-10-08 15:32:27 +08:00
Sebastien Bourdeauducq 3fa5d0b963 wrpll: clean up sign extension 2020-10-08 15:32:27 +08:00
hartytp 87911810d6 wrpll.core: add CSRs to monitor the collector outputs 2020-10-08 15:32:27 +08:00
hartytp f2f942a8b4 wrpll.ddmtd: remove CSRs from DDMTD 
We will gather then from the collector output so we can get all tags on the same cycle
 2020-10-08 15:32:27 +08:00
hartytp 85bb641917 wrpll.ddmtd: fix first edge deglitcher 
The blind counter should be held in reset whenever the input is high,
not just when there is a rising edge (otherwise the counter runs down
during the main pulse and can then re-trigger on jitter from the falling edge)
 2020-10-08 15:32:27 +08:00
hartytp f3cd0fc675 wrpll.filters: the helper clipping threshold is currently way too low. Move clipping after the bitshift to increase a bit. 
TODO: think about this and pick a sensible threshold (and also think about integrator anti windup)
 2020-10-08 15:32:27 +08:00
hartytp e5e648bde1 wrpll: add bit shift for collector helper output 2020-10-08 15:32:27 +08:00
hartytp c9ae406ac6 wrpll: change the DDMTD helper frequency to match CERN, improve docs 2020-10-08 15:32:27 +08:00
hartytp f6f6045f1a wrpll.thls: fix make 2020-10-08 15:32:27 +08:00
hartytp b44b870452 wrpll.filters: update to match Weida's MatLab simulations 2020-10-08 15:32:27 +08:00
hartytp e9ab434fa7 wrpll.core: update for modified collector 2020-10-08 15:32:27 +08:00
Sebastien Bourdeauducq 17c952b8fb wrpll: style 2020-10-08 15:32:27 +08:00
hartytp ebb7ccbfd1 wrpll: document DDMTD collector and fix unwrapping 2020-10-08 15:32:27 +08:00
cw-mlabs e4b16428f5 wrpll: fix run signal 2020-07-27 13:02:02 +08:00
cw-mlabs 8dd9a6d024 wrpll: fix scl signal 2020-07-27 12:59:32 +08:00
Sebastien Bourdeauducq dfa033eb87 wrpll: new collector from Weida/Tom 2020-01-24 10:31:52 +08:00
Sebastien Bourdeauducq dee16edb78 wrpll: DDMTD sampler double latching 2020-01-22 19:16:26 +08:00
Sebastien Bourdeauducq 6c3e71a83a wrpll: cleanup 2020-01-18 09:43:43 +08:00
Sebastien Bourdeauducq 344f8bd12a wrpll: collector patch from Weida 2020-01-18 09:42:58 +08:00
Sebastien Bourdeauducq 50302d57c0 wrpll: more careful I2C timing 2020-01-14 20:03:46 +08:00
Sebastien Bourdeauducq 105dd60c78 wrpll: ADPLLProgrammer mini test bench and fixes 2020-01-14 16:52:25 +08:00
Sebastien Bourdeauducq 3242e9ec6c wrpll: loop test 2020-01-13 22:31:57 +08:00
Sebastien Bourdeauducq 8ec0f2e717 wrpll: implement ADPLLProgrammer 2020-01-13 22:30:11 +08:00
Sebastien Bourdeauducq d685619bcd wrpll: collector code modifications from Weida 2020-01-13 20:42:41 +08:00
Sebastien Bourdeauducq a666766f38 wrpll: add ADPLL offset registers 2019-12-30 22:19:42 +08:00
Sebastien Bourdeauducq 5c6e394928 ddmtd: add collector 2019-12-30 22:17:44 +08:00
Sebastien Bourdeauducq f57f235dca wrpll: new frequency meter 
As per Mattermost discussion with Tom.
 2019-12-30 19:47:57 +08:00
Sebastien Bourdeauducq 9e15ff7e6a wrpll: improve DDMTD deglitcher 2019-12-30 16:56:06 +08:00
Sebastien Bourdeauducq 05e2e1899a wrpll: update OBUFDS_GTE2 comment 
Seems O can fan out simultaneously to transceiver and fabric.
Kasli is using ODIV2 for no particular reason.
 2019-12-09 11:58:54 +08:00
Sebastien Bourdeauducq 4148efd2ee wrpll: implement filters and connect to Si549 2019-12-09 11:47:29 +08:00
Sebastien Bourdeauducq d43fe644f0 wrpll: stabilize DDMTDSamplerGTP 2019-12-09 11:47:14 +08:00
Sebastien Bourdeauducq 0499f83580 wrpll: helper clock sanity check 2019-12-08 23:46:33 +08:00
Sebastien Bourdeauducq 46a776d06e sayma: introduce WRPLL on RTM 2019-12-08 15:30:00 +08:00
Sebastien Bourdeauducq da9237de53 wrpll: support differential DDMTD inputs 2019-12-07 18:18:57 +08:00
Sebastien Bourdeauducq 7098854b0f wrpll: share DDMTD counter 2019-12-04 19:05:56 +08:00
Sebastien Bourdeauducq eb271f383b wrpll: add DDMTD cores 2019-11-28 22:03:50 +08:00
Sebastien Bourdeauducq 2e55e39ac7 wrpll: use spaces to indent 2019-11-28 17:40:25 +08:00
Sebastien Bourdeauducq 354d82cfe3 wrpll: drive helper clock domain 2019-11-28 17:40:00 +08:00
Sebastien Bourdeauducq fe0c324b38 sayma: integrate si549 core 2019-11-20 17:37:16 +08:00
Sebastien Bourdeauducq fa41c946ea wrpll: si549 fixes 2019-11-20 17:04:24 +08:00
Sebastien Bourdeauducq c5dbab1929 gateware: move wrpll to drtio 2019-11-20 14:43:08 +08:00