ad099edf63
kasli: integrate grabber
2018-05-28 22:43:40 +08:00
b20a8c86b0
kasli: don't bother with grabber ttls for now
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not used on target cameras
2018-05-28 07:31:00 +02:00
80c69da17e
eem: add Grabber IOs and CC
2018-05-28 11:16:23 +08:00
b09d07905c
kasli: add LUH/PTB/HUB variants
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and refactor/simplify variant selection
2018-05-27 18:33:27 +00:00
Florent Kermarrec
bca2969957
sayma_rtm: add RTMScratch module to test remote Wishbone accesses
2018-05-24 16:53:10 +02:00
19efd8b13e
kasli: refactor EEM code
2018-05-24 18:41:54 +08:00
4e5fe672e7
kasli: add tester target
2018-05-21 17:43:39 +08:00
72aef5799e
kasli/ustc: use TTLOut
2018-05-18 22:55:28 +08:00
b10d3ee4b4
make RTIO clock switch optional and simplify
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Kasli no longer has an internal RTIO clock.
Switching clocks dynamically is no longer supported.
2018-05-18 17:41:34 +08:00
8a988d0feb
kasli: remove leftover debug print
2018-05-18 17:25:23 +08:00
37bd0c2566
kasli: add USTC target
2018-05-18 16:15:07 +08:00
Florent Kermarrec
f8a9dd930b
serwb/genphy: add device parameter (not used here, but this way all the phys share the same parameters), scrambling is also now always enabled.
2018-05-15 23:51:14 +02:00
Florent Kermarrec
c18a73d45f
sayma_amc/rtm: use new serwb low-speed phy
2018-05-15 16:40:50 +02:00
27f975e7bb
kasli: eem DifferentialInputs need DIFF_TERM
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cleanup some formatting on the way
2018-05-14 12:26:49 +00:00
whitequark
ee4c475cf3
gateware: fix Sayma satellite build.
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RTIO clock multiplier was removed from Sayma in 32f22f4c
2018-05-13 13:10:39 +00:00
8c1390e557
kasli: use 62.5MHz clock for siphaser reference ( #999 )
2018-05-12 22:58:03 +08:00
6b811c1a8b
sayma: fix runtime/rtm gateware address conflict
2018-05-09 19:47:29 +08:00
7d4a103a43
opticlock, suservo: set default kasli hw_rev
2018-05-07 09:07:18 +02:00
whitequark
b1d349cc1b
firmware: implement a sampling profiler.
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Does not yet support constructing call graphs.
2018-05-05 00:44:40 +00:00
Florent Kermarrec
05955bfd79
sayma_rtm: use bufio for sys4x (needed since we are using a -1 speedgrade)
2018-05-01 22:16:35 +02:00
Florent Kermarrec
84e1f05559
sayma_rtm: make cd_sys4x clock domain reset_less
2018-05-01 16:11:26 +02:00
5a683ddd1f
Revert "kasli: force hw_rev for the different targets"
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This reverts commit 17d7d7856a
2018-04-28 23:24:41 +02:00
17d7d7856a
kasli: force hw_rev for the different targets
2018-04-28 21:30:29 +02:00
5d3c76fd50
sayma_rtm: use bitstream opts in migen
2018-04-27 15:43:32 +00:00
307cd07b9d
suservo: lots of gateware/ runtime changes
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tested/validated:
* servo enable/disable
* dds interface, timing, io_update, mask_nu
* channel control (en_out, en_iir, profile)
* profile configuration (coefficients, delays, offsets, channel)
* adc timings and waveforms measured
* asf state readback
* adc readback
individual changes below:
suservo: correct rtio readback
suservo: example, device_db [wip]
suservo: change rtio channel layout
suservo: mem ports in rio domain
suservo: sck clocked from rio_phy
suservo: cleanup, straighten out timing
suservo: dds cs polarity
suservo: simplify pipeline
suservo: drop unused eem names
suservo: decouple adc SR from IIR
suservo: expand coredevice layer
suservo: start the correct stage
suservo: actually load ctrl
suservo: refactor/tweak adc timing
suservo: implement cpld and dds init
2018-04-27 13:50:26 +02:00
Florent Kermarrec
8212e46f5e
sayma_amc: filter jesd refclk/sysref with jreset (hmc7043 can generate noise when unconfigured see sinara issue #541 )
2018-04-27 13:04:37 +02:00
f9b2c32739
suservo: add pgia spi channel
2018-04-25 17:14:25 +00:00
37c186a0fc
suservo: refactor, constrain
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* remove DiffMixin, move pad layout handling to pads
* add input delay constraints, IDELAYs
2018-04-25 13:44:52 +00:00
d0258b9b2d
suservo: set input delays
2018-04-24 15:30:25 +00:00
3942c2d274
suservo: fix clkout cd drive
2018-04-24 10:18:32 +00:00
f74998a5e0
suservo: move arch logic to top, fix tests
2018-04-23 21:11:26 +00:00
929ed4471b
kasli/SUServo: use suservo, implement urukul_qspi
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m-labs/artiq#788
2018-04-23 18:30:18 +00:00
Florent Kermarrec
439d2bf2bc
sayma/serwb: adapt, full reset of rtm on link reset
2018-04-17 19:24:03 +02:00
eac447278f
kasli: add MITLL variant
2018-04-17 19:00:11 +08:00
756e120c27
kasli/sysu: add comments
2018-04-17 18:46:55 +08:00
Florent Kermarrec
1acd7ea1db
sayma/serwb: re-enable scrambling
2018-04-17 00:49:36 +02:00
Florent Kermarrec
ca01c8f1cb
sayma: reduce serwb linerate to 500Mbps
2018-04-16 23:19:15 +02:00
Florent Kermarrec
bb90fb7d59
sayma/serwb: remove scrambling (does not seems to work on sayma for now...)
2018-04-07 15:57:57 +02:00
Florent Kermarrec
e15f8aa903
sayma/serwb: enable scrambling
2018-04-07 14:52:37 +02:00
Florent Kermarrec
2f8bd022f7
sayma_rtm: remove sys0p2x clock
2018-04-07 03:10:34 +02:00
Florent Kermarrec
73b727cade
serwb: new version using only sys/sys4x clocks domains, scrambling deactivated.
2018-04-07 02:59:14 +02:00
Florent Kermarrec
dd21c07b85
targets/sayma_rtm: fix serwb 2 ...
2018-04-03 18:59:05 +02:00
Florent Kermarrec
7488703f23
targets/sayma_rtm: fix serwb
2018-04-03 18:57:00 +02:00
Florent Kermarrec
aef0153a8f
targets/sayma: adapt to new serwb clocking
2018-04-03 18:53:39 +02:00
493d2a653f
siphaser: add false path between sys_clk and mmcm_freerun_output
2018-03-29 10:55:41 +08:00
4229c045f4
kasli: fix DRTIO master clock constraint
2018-03-29 10:20:31 +08:00
3d89ba2e11
sayma: remove debug leftover
2018-03-29 10:20:17 +08:00
605292535c
kasli: ignore OSERDESE2->ISERDESE2 timing path on DRTIO targets as well
2018-03-29 10:12:02 +08:00
3a0dfb7fdc
ad53xx: port monitor, moninj dashboard, kc705 target
2018-03-24 16:04:02 +01:00
770b0a7b79
novogorny: conv -> cnv
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* parity with sampler
* also add novogorny device to opticlock
2018-03-21 18:38:42 +00:00
1afce8c613
kasli: simplify single eem pin formatting
2018-03-21 13:08:42 +01:00
d48b8f3086
kasli: fix sampler sdr/cnv pins
2018-03-21 09:28:00 +00:00
1fb5907362
kasli: add SUServo variant (Sampler-Urukul Servo)
2018-03-21 08:53:26 +00:00
f74d5772f4
sampler: add wide eem definition
2018-03-21 08:53:26 +00:00
32f22f4c9c
sayma: disable SERDES TTL entirely
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Timing closure becomes very random, even at 4X.
2018-03-21 13:03:48 +08:00
f8c2d54e75
ttl_serdes_ultrascale: configurable SERDES ratio. Also try X4 on Sayma
2018-03-21 13:01:38 +08:00
9c2d343052
sayma: use SERDES RTIO TTL
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This is not enabled on the standalone design as it breaks timing.
2018-03-21 10:53:52 +08:00
Thomas Harty
37d431039d
Fix typos.
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Reduce ififo depth to 4 for Zotino.
2018-03-19 09:42:18 +00:00
Thomas Harty
c4fa44bc62
Add Zotino and Sampler functions to Kasli. Add Zotino to Kasli EEM 7 on OptiClock.
2018-03-18 00:25:43 +00:00
Florent Kermarrec
eb6e59b44c
sayma_rtm: fix serwb timing constraints (was causing the gated clock warning)
2018-03-12 11:25:29 +01:00
fc3d97f1f7
drtio: remove spurious multichannel transceiver clock constraints
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They used to cause (otherwise harmless) Vivado critical warnings.
2018-03-09 22:46:27 +08:00
caf7b14b55
kasli: generate fine RTIO clock in DRTIO targets, separate RTIO channel code
2018-03-09 22:36:16 +08:00
82831a85b6
kasli/opticlock: add eem6 phys
2018-03-07 21:32:59 +01:00
916197c4d7
siphaser: cleanup
2018-03-07 11:15:44 +08:00
7d98864b31
sayma: enable siphaser
2018-03-07 10:57:30 +08:00
a6e29462a8
sayma: enable multilink DRTIO
2018-03-07 10:57:30 +08:00
c34d00cbc9
drtio: implement Si5324 phaser gateware and partial firmware support
2018-03-07 10:57:30 +08:00
994ceca9ff
sayma_amc: disable slave fpga gateware loading
2018-03-06 17:27:43 +01:00
62af7fe2ac
Revert "kasli/opticlock: use plain ttls for channels 8-23"
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This reverts commit bd5c222569eb68d624a5ac1e9f2542f6ee553f83.
No decrease in power consumption or improvement in timing.
2018-03-06 14:27:19 +01:00
fd3cdce59a
kasli/opticlock: use plain ttls for channels 8-23
2018-03-06 14:27:19 +01:00
956098c213
kasli: add second urukul, make clk_sel drive optional
2018-03-06 14:26:27 +01:00
07de7af86a
kasli: make second eem optional in urukul
2018-03-06 14:26:26 +01:00
ddcc68cff9
sayma_amc: move bitstream options to migen
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close #930
2018-03-02 18:13:03 +08:00
a9daaad77b
kasli: add SYSU variant and device_db
2018-03-02 14:44:31 +08:00
ec5b81da55
kc705: switch backplane spi to spi2
2018-03-01 11:19:18 +01:00
a7720d05cd
firmware, sayma: port converter_spi to spi2
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* ksupport/nrt_bus
* port ad9154, hmc830, hmc7043
* port local_spi and drtio_spi
* port kernel_proto libdrtioaux, satman
* change sayma_rtm gateware over
* add spi2 NRTSPIMaster
* remove spi NRTSPIMaster
* change sayma device_db
* change HMC830 to open mode and explicitly sequence open mode
2018-03-01 11:19:18 +01:00
54984f080b
artiq_flash: flash RTM firmware
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based on whitequark's work in f95fb27m-labs/artiq#813
2018-02-28 19:29:01 +01:00
1f999c7f5f
sayma_amc: expose RTM fpga load pins as GPIOs
2018-02-28 18:44:36 +01:00
386aa75aaa
kasli: control SFP1 and SFP2 LEDs in DRTIO satellite to match master
2018-02-27 23:18:18 +08:00
5d81877b34
kasli: implement multi-link DRTIO on SFP1 and SFP2 of master
2018-02-27 23:15:20 +08:00
e565d3fa59
kasli: add analyzer and RTIO log to DRTIO master target
2018-02-27 18:09:07 +08:00
1452cd7447
novogorny: add coredevice driver and test with Kasli
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m-labs/artiq#687
2018-02-22 17:19:51 +01:00
3b7971d15d
kasli: spelling
2018-02-22 17:19:51 +01:00
771bf87b56
kc705: port amc101_dac/spi0 and sma_spi to spi2
2018-02-22 17:19:51 +01:00
f8e6b4f4e3
ad5360: port to spi2
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* kc705 nist_clock target gateware
* coredevice driver
* moninj code
* test/example/device_db
This is untested as we don't have a AD5360 board right now.
Will be tested with Zotino v1.1
m-labs/artiq#926
2018-02-22 10:25:46 +01:00
fa0d929b4d
drtio: reorganize RX synchronizers
2018-02-22 15:21:23 +08:00
e5de5ef473
kasli: use deterministic RX synchronizer
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Could not reproduce the "fully broken bitstream" bug.
2018-02-22 15:18:09 +08:00
a5ad1dc266
kc705: fix sdcard miso pullup
2018-02-21 19:41:05 +01:00
0d8145084d
test_spi: move to new spi2 core
2018-02-21 19:41:05 +01:00
a63fd306af
urukul: use spi2
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* switch kc705 and kasli targets to spi2 gateware on urukul
* rewrite urukul, ad9912, ad9910
* update example experiments, device_dbs
2018-02-21 15:00:28 +00:00
91a4a7b0ee
kasli: free run si5324 on opticlock for now
2018-02-21 13:37:29 +00:00
7e02d8245c
kasli: false paths
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* don't bother with the round trip OSERDESE2 -> ... -> pad -> ... ->
ISERDESE2
* clock groups with derived clocks c.f. migen 9c3a301
2018-02-19 13:05:11 +00:00
0f4549655b
sayma: use Xilinx RX synchronizer
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Cannot be used on Kasli, this breaks the bitstream entirely (nothing on UART).
2018-02-19 17:49:53 +08:00
3bc575bee7
drtio: add missing define for Sayma master
2018-02-19 17:11:21 +08:00
7376ab0ff8
drtio: fix Sayma after 83abdd28
2018-02-19 17:10:55 +08:00
c329c83676
kasli: fix disable_si5324_ibuf no_retiming
2018-02-19 12:19:05 +08:00
a93decdef2
kasli: disable DRTIO IBUFDS_GTE2 until Si5324 is initialized
2018-02-19 00:48:37 +08:00
83abdd283a
drtio: signal stable clock input to transceiver
2018-02-18 22:29:30 +08:00
287d533437
Revert "sayma_amc: remove RTM bitstream upload core. Closes #908 "
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This reverts commit 2d4a1340ea
2018-02-17 17:38:48 +08:00
73985a9215
sayma: remove constraints at outputs of serwb PLL (see misoc d1489ed)
2018-02-17 17:38:17 +08:00
