* if multiple RTIO channels influence the same data stream and physical
output channel (see SAWG) differential latency needs to be compensated
* this is a NOP for phys with zero delay (default)
* if delay==1, it adds one timestamp-wide register
* if delay >1, it adds one adder and one register
* latency compensation using (~10-50 deep) delay lines is about as
expensive as a single adder+register but very tedious to implement
Back when RTIO was driving TTLs, this functionality made it simpler to use by removing some irrelevant underflows.
The same technique is not applicable to DDS and SPI, so the user will have to deal with such underflows.
This patch makes the behavior of RTIO more consistent and the code simpler.
