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fmcdio_vhdci_eem: fix direction shift register permutation and polarity

This commit is contained in:
Sebastien Bourdeauducq 2018-07-19 14:10:36 +08:00
parent e71cbe53a6
commit fe93a454d6
1 changed files with 11 additions and 2 deletions
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13
artiq/coredevice/fmcdio_vhdci_eem.py
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@ -6,11 +6,20 @@ eem_fmc_connections = {
} }
fmcdio_shiftreg_permutation = [
1, 0, 3, 2, 5, 4, 7, 6,
9, 8, 11, 10, 13, 12, 15, 14,
17, 16, 19, 18, 21, 20, 23, 22,
25, 24, 27, 26, 29, 28, 31, 30
]
def shiftreg_bits(eem, out_pins): def shiftreg_bits(eem, out_pins):
r = 0 r = 0
for i in range(8): for i in range(8):
if i in out_pins: if i not in out_pins:
shift = eem_fmc_connections[eem][i] lvds_line = eem_fmc_connections[eem][i]
shift = fmcdio_shiftreg_permutation.index(lvds_line)
r |= 1 << shift r |= 1 << shift
return r return r