From fd16be6f732b8dea5e0f50e7f88309a96e52f1c3 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Wed, 13 Aug 2014 18:37:01 +0800
Subject: [PATCH] sim/devices: remove implicit core

---
 artiq/sim/devices.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/artiq/sim/devices.py b/artiq/sim/devices.py
index c5ec905f7..042f98475 100644
--- a/artiq/sim/devices.py
+++ b/artiq/sim/devices.py
@@ -10,6 +10,7 @@ class Core:
 
 class Input(AutoContext):
 	parameters = "name"
+	implicit_core = False
 
 	def build(self):
 		self.prng = Random()
@@ -27,6 +28,7 @@ class Input(AutoContext):
 
 class WaveOutput(AutoContext):
 	parameters = "name"
+	implicit_core = False
 
 	def pulse(self, frequency, duration):
 		time.manager.event(("pulse", self.name, frequency, duration))
@@ -34,6 +36,7 @@ class WaveOutput(AutoContext):
 
 class VoltageOutput(AutoContext):
 	parameters = "name"
+	implicit_core = False
 
 	def set(self, value):
 		time.manager.event(("set_voltage", self.name, value))