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artiq_ddb_template: fix clk_div config 

remove clk_div default in jsonschema
set CLK IN divided by 1 as default when bypassing PLL
This commit is contained in:
morgan 2024-02-16 15:14:01 +08:00 committed by Sébastien Bourdeauducq
parent 795b8ae4c6
commit fc282d4e17
2 changed files with 9 additions and 5 deletions
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3
artiq/coredevice/coredevice_generic.schema.json
View File

@ -308,8 +308,7 @@
"clk_div": { "clk_div": {
"type": "integer", "type": "integer",
"minimum": 0, "minimum": 0,
"maximum": 3, "maximum": 3
"default": 0
}, },
"pll_n": { "pll_n": {
"type": "integer" "type": "integer"

11
artiq/frontend/artiq_ddb_template.py
View File

@ -211,6 +211,11 @@ class PeripheralManager:
urukul_name = self.get_name("urukul") urukul_name = self.get_name("urukul")
synchronization = peripheral["synchronization"] synchronization = peripheral["synchronization"]
channel = count(0) channel = count(0)
pll_en = peripheral["pll_en"]
clk_div = peripheral.get("clk_div")
if clk_div is None:
clk_div = 0 if pll_en else 1
self.gen(""" self.gen("""
device_db["eeprom_{name}"] = {{ device_db["eeprom_{name}"] = {{
"type": "local", "type": "local",
@ -277,7 +282,7 @@ class PeripheralManager:
sync_device="\"ttl_{name}_sync\"".format(name=urukul_name) if synchronization else "None", sync_device="\"ttl_{name}_sync\"".format(name=urukul_name) if synchronization else "None",
refclk=peripheral.get("refclk", self.primary_description["rtio_frequency"]), refclk=peripheral.get("refclk", self.primary_description["rtio_frequency"]),
clk_sel=peripheral["clk_sel"], clk_sel=peripheral["clk_sel"],
clk_div=peripheral["clk_div"]) clk_div=clk_div)
dds = peripheral["dds"] dds = peripheral["dds"]
pll_vco = peripheral.get("pll_vco") pll_vco = peripheral.get("pll_vco")
for i in range(4): for i in range(4):
@ -299,7 +304,7 @@ class PeripheralManager:
uchn=i, uchn=i,
sw=",\n \"sw_device\": \"ttl_{name}_sw{uchn}\"".format(name=urukul_name, uchn=i) if len(peripheral["ports"]) > 1 else "", sw=",\n \"sw_device\": \"ttl_{name}_sw{uchn}\"".format(name=urukul_name, uchn=i) if len(peripheral["ports"]) > 1 else "",
pll_vco=",\n \"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "", pll_vco=",\n \"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "",
pll_n=peripheral.get("pll_n", 32), pll_en=peripheral["pll_en"], pll_n=peripheral.get("pll_n", 32), pll_en=pll_en,
sync_delay_seed=",\n \"sync_delay_seed\": \"eeprom_{}:{}\"".format(urukul_name, 64 + 4*i) if synchronization else "", sync_delay_seed=",\n \"sync_delay_seed\": \"eeprom_{}:{}\"".format(urukul_name, 64 + 4*i) if synchronization else "",
io_update_delay=",\n \"io_update_delay\": \"eeprom_{}:{}\"".format(urukul_name, 64 + 4*i) if synchronization else "") io_update_delay=",\n \"io_update_delay\": \"eeprom_{}:{}\"".format(urukul_name, 64 + 4*i) if synchronization else "")
elif dds == "ad9912": elif dds == "ad9912":
@ -320,7 +325,7 @@ class PeripheralManager:
uchn=i, uchn=i,
sw=",\n \"sw_device\": \"ttl_{name}_sw{uchn}\"".format(name=urukul_name, uchn=i) if len(peripheral["ports"]) > 1 else "", sw=",\n \"sw_device\": \"ttl_{name}_sw{uchn}\"".format(name=urukul_name, uchn=i) if len(peripheral["ports"]) > 1 else "",
pll_vco=",\n \"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "", pll_vco=",\n \"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "",
pll_n=peripheral.get("pll_n", 8), pll_en=peripheral["pll_en"]) pll_n=peripheral.get("pll_n", 8), pll_en=pll_en)
else: else:
raise ValueError raise ValueError
return next(channel) return next(channel)