From fbf05db5abed2dee6502a3b35b5c00894a6850df Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Robert=20J=C3=B6rdens?= <rj@quartiq.de>
Date: Wed, 29 Aug 2018 16:22:00 +0000
Subject: [PATCH] kasli: add VLBAI Master and Satellite

---
 artiq/gateware/targets/kasli.py | 58 ++++++++++++++++++++++++++++++++-
 1 file changed, 57 insertions(+), 1 deletion(-)

diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py
index 744bb983b..d6d7296ea 100755
--- a/artiq/gateware/targets/kasli.py
+++ b/artiq/gateware/targets/kasli.py
@@ -878,6 +878,62 @@ class Satellite(_SatelliteBase):
         self.add_rtio(self.rtio_channels)
 
 
+class VLBAIMaster(_MasterBase):
+    def __init__(self, hw_rev=None, *args, **kwargs):
+        if hw_rev is None:
+            hw_rev = "v1.1"
+        _MasterBase.__init__(self, rtio_clk_freq=125e6, hw_rev=hw_rev, *args,
+                             **kwargs)
+
+        self.rtio_channels = []
+        eem.DIO.add_std(self, 0,
+            ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
+        eem.DIO.add_std(self, 1,
+            ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
+        eem.DIO.add_std(self, 2,
+            ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
+        eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X)
+        eem.Urukul.add_std(self, 5, 4, ttl_serdes_7series.Output_8X)
+        eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X)
+        eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X)
+
+        phy = ttl_simple.Output(self.platform.request("user_led", 0))
+        self.submodules += phy
+        self.rtio_channels.append(rtio.Channel.from_phy(phy))
+
+        self.config["HAS_RTIO_LOG"] = None
+        self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
+        self.rtio_channels.append(rtio.LogChannel())
+
+        self.add_rtio(self.rtio_channels)
+
+
+class VLBAISatellite(_SatelliteBase):
+    def __init__(self, hw_rev=None, *args, **kwargs):
+        if hw_rev is None:
+            hw_rev = "v1.1"
+        _SatelliteBase.__init__(self, rtio_clk_freq=125e6, hw_rev=hw_rev,
+                                *args, **kwargs)
+
+        self.rtio_channels = []
+        eem.DIO.add_std(self, 0,
+            ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
+        eem.DIO.add_std(self, 1,
+            ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
+        eem.DIO.add_std(self, 2,
+            ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
+        eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X)
+        eem.Urukul.add_std(self, 5, 4, ttl_serdes_7series.Output_8X)
+        eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X)
+        eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X)
+
+        phy = ttl_simple.Output(self.platform.request("user_led", 0))
+        self.submodules += phy
+        self.rtio_channels.append(rtio.Channel.from_phy(phy))
+
+        self.add_rtio(self.rtio_channels)
+
+
 def main():
     parser = argparse.ArgumentParser(
         description="ARTIQ device binary builder for Kasli systems")
@@ -886,7 +942,7 @@ def main():
     parser.set_defaults(output_dir="artiq_kasli")
     variants = {cls.__name__.lower(): cls for cls in [
         Opticlock, SUServo, SYSU, MITLL, USTC, Tsinghua, WIPM, PTB, HUB, LUH,
-        Tester, Master, Satellite]}
+        VLBAIMaster, VLBAISatellite, Tester, Master, Satellite]}
     parser.add_argument("-V", "--variant", default="opticlock",
                         help="variant: {} (default: %(default)s)".format(
                             "/".join(sorted(variants.keys()))))