From f8e4cc37d0c570084b8396541a1655aa2c72c029 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sun, 6 Oct 2019 20:15:27 +0800
Subject: [PATCH] sayma_rtm: reset and detect DACs

---
 artiq/firmware/satman/main.rs       | 20 +++++++++++++-------
 artiq/gateware/targets/sayma_rtm.py |  3 +++
 2 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/artiq/firmware/satman/main.rs b/artiq/firmware/satman/main.rs
index b0c41543f..e9cc3c1ed 100644
--- a/artiq/firmware/satman/main.rs
+++ b/artiq/firmware/satman/main.rs
@@ -423,6 +423,12 @@ pub extern fn main() -> i32 {
     #[cfg(has_hmc830_7043)]
     /* must be the first SPI init because of HMC830 SPI mode selection */
     hmc830_7043::init().expect("cannot initialize HMC830/7043");
+    #[cfg(has_ad9154)]
+    {
+        for dacno in 0..csr::CONFIG_AD9154_COUNT {
+            board_artiq::ad9154::reset_and_detect(dacno as u8).expect("AD9154 DAC not detected");
+        }
+    }
     #[cfg(has_allaki_atts)]
     board_artiq::hmc542::program_all(8/*=4dB*/);
 
@@ -451,7 +457,7 @@ pub extern fn main() -> i32 {
         si5324::siphaser::select_recovered_clock(true).expect("failed to switch clocks");
         si5324::siphaser::calibrate_skew().expect("failed to calibrate skew");
 
-        #[cfg(has_ad9154)]
+        #[cfg(has_jdcg)]
         {
             /*
              * One side of the JESD204 elastic buffer is clocked by the Si5324, the other
@@ -466,8 +472,8 @@ pub extern fn main() -> i32 {
              * To handle those cases, we simply keep the JESD204 core in reset unless the
              * Si5324 is locked to the recovered clock.
              */
-            board_artiq::ad9154::jesd_reset(false);
-            board_artiq::ad9154::init();
+            board_artiq::jdcg::jesd_reset(false);
+            // TODO: board_artiq::ad9154::init();
         }
 
         drtioaux::reset(0);
@@ -483,7 +489,7 @@ pub extern fn main() -> i32 {
             hardware_tick(&mut hardware_tick_ts);
             if drtiosat_tsc_loaded() {
                 info!("TSC loaded from uplink");
-                #[cfg(has_ad9154)]
+                /* TODO: #[cfg(has_jdcg)]
                 {
                     if let Err(e) = board_artiq::jesd204sync::sysref_auto_rtio_align() {
                         error!("failed to align SYSREF at FPGA: {}", e);
@@ -491,7 +497,7 @@ pub extern fn main() -> i32 {
                     if let Err(e) = board_artiq::jesd204sync::sysref_auto_dac_align() {
                         error!("failed to align SYSREF at DAC: {}", e);
                     }
-                }
+                } */
                 for rep in repeaters.iter() {
                     if let Err(e) = rep.sync_tsc() {
                         error!("failed to sync TSC ({})", e);
@@ -503,8 +509,8 @@ pub extern fn main() -> i32 {
             }
         }
 
-        #[cfg(has_ad9154)]
-        board_artiq::ad9154::jesd_reset(true);
+        #[cfg(has_jdcg)]
+        board_artiq::jdcg::jesd_reset(true);
 
         drtiosat_reset_phy(true);
         drtiosat_reset(true);
diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py
index 5c0be328d..350a4b74d 100755
--- a/artiq/gateware/targets/sayma_rtm.py
+++ b/artiq/gateware/targets/sayma_rtm.py
@@ -203,8 +203,11 @@ class Satellite(_SatelliteBase):
             platform.request("hmc7043_gpo"))
         self.csr_devices.append("hmc7043_gpo")
         self.config["HAS_HMC830_7043"] = None
+        self.config["HAS_AD9154"] = None
+        self.config["AD9154_COUNT"] = 2
         self.config["CONVERTER_SPI_HMC830_CS"] = 0
         self.config["CONVERTER_SPI_HMC7043_CS"] = 1
+        self.config["CONVERTER_SPI_FIRST_AD9154_CS"] = 2
         self.config["HMC830_REF"] = "150"
 
         # HMC workarounds