From f7427dda395d85c19f2c28ce0aa01534eb506f92 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Sun, 28 Jun 2015 20:08:39 -0600 Subject: [PATCH] test: make benchmarks unittest --- artiq/test/coredevice.py | 150 ++++++++++++++++++++++--------- artiq/test/hardware_testbench.py | 3 +- 2 files changed, 109 insertions(+), 44 deletions(-) diff --git a/artiq/test/coredevice.py b/artiq/test/coredevice.py index 78d30142a..552fc26e1 100644 --- a/artiq/test/coredevice.py +++ b/artiq/test/coredevice.py @@ -1,56 +1,120 @@ -from artiq import * -from artiq.test.hardware_testbench import * +from math import sqrt + +from artiq.language import * +from artiq.test.hardware_testbench import ExperimentCase from artiq.coredevice.runtime_exceptions import RTIOUnderflow -class RTTTest(ExperimentCase): - class RTT(Experiment, AutoDB): - class DBKeys: - core = Device() - ttl_inout = Device() - rtt = Result() +class RTT(Experiment, AutoDB): + class DBKeys: + core = Device() + ttl_inout = Device() + rtt = Result() - @kernel - def run(self): - self.ttl_inout.output() - delay(1*us) - t0 = now() - with parallel: - self.ttl_inout.gate_falling(2*us) + @kernel + def run(self): + self.ttl_inout.output() + delay(1*us) + with parallel: + self.ttl_inout.gate_rising(2*us) + with sequential: + delay(1*us) + t0 = now() self.ttl_inout.pulse(1*us) - self.rtt = self.ttl_inout.timestamp() - t0 + self.rtt = self.ttl_inout.timestamp() - t0 + +class Loopback(Experiment, AutoDB): + class DBKeys: + core = Device() + loop_in = Device() + loop_out = Device() + rtt = Result() + + @kernel + def run(self): + with parallel: + self.loop_in.gate_rising(2*us) + with sequential: + delay(1*us) + t0 = now() + self.loop_out.pulse(1*us) + self.rtt = self.loop_in.timestamp() - t0 + + +class PulseRate(Experiment, AutoDB): + class DBKeys: + core = Device() + loop_out = Device() + pulse_rate = Result() + + @kernel + def run(self): + dt = time_to_cycles(1000*ns) + while True: + try: + for i in range(1000): + self.loop_out.pulse(cycles_to_time(dt)) + delay(cycles_to_time(dt)) + except RTIOUnderflow: + dt += 1 + self.core.break_realtime() + else: + self.pulse_rate = cycles_to_time(2*dt) + break + + +class CoredeviceTest(ExperimentCase): def test_rtt(self): - rtt = self.execute(self.RTT)["rtt"] + rtt = self.execute(RTT)["rtt"] + print(rtt) + self.assertGreater(rtt, 0*ns) + self.assertLess(rtt, 100*ns) + + def test_loopback(self): + rtt = self.execute(Loopback)["rtt"] + print(rtt) self.assertGreater(rtt, 0*ns) self.assertLess(rtt, 40*ns) - -class PulseRateTest(ExperimentCase): - class PulseRate(Experiment, AutoDB): - class DBKeys: - core = Device() - loop_out = Device() - pulse_rate = Result() - - @kernel - def run(self): - dt = time_to_cycles(1000*ns) - while True: - try: - for i in range(1000): - self.loop_out.pulse(cycles_to_time(dt)) - delay(cycles_to_time(dt)) - except RTIOUnderflow: - dt += 1 - self.core.break_realtime() - else: - self.pulse_rate = cycles_to_time(2*dt) - break - - def test_rate(self): - rate = self.execute(self.PulseRate)["pulse_rate"] + def test_pulse_rate(self): + rate = self.execute(PulseRate)["pulse_rate"] + print(rate) self.assertGreater(rate, 100*ns) - self.assertLess(rate, 2000*ns) + self.assertLess(rate, 2500*ns) +class RPCTiming(Experiment, AutoDB): + class DBKeys: + core = Device() + repeats = Argument(100) + rpc_time_mean = Result() + rpc_time_stddev = Result() + + def nop(self, x): + pass + + @kernel + def bench(self): + self.ts = [0. for _ in range(self.repeats)] + for i in range(self.repeats): + t1 = self.core.get_rtio_time() + self.nop(1) + t2 = self.core.get_rtio_time() + self.ts[i] = t2 - t1 + + def run(self): + self.bench() + mean = sum(self.ts)/self.repeats + self.rpc_time_stddev = sqrt( + sum([(t - mean)**2 for t in self.ts])/self.repeats)*s + self.rpc_time_mean = mean*s + + +class RPCTest(ExperimentCase): + def test_rpc_timing(self): + res = self.execute(RPCTiming) + print(res) + self.assertGreater(res["rpc_time_mean"], 100*ns) + self.assertLess(res["rpc_time_mean"], 10*ms) + self.assertLess(res["rpc_time_stddev"], 1*ms) diff --git a/artiq/test/hardware_testbench.py b/artiq/test/hardware_testbench.py index 35bb100e9..bdb1e2e82 100644 --- a/artiq/test/hardware_testbench.py +++ b/artiq/test/hardware_testbench.py @@ -3,7 +3,7 @@ import sys import unittest import logging -from artiq import * +from artiq.language import * from artiq.protocols.file_db import FlatFileDB from artiq.master.worker_db import DBHub, ResultDB from artiq.frontend.artiq_run import ( @@ -33,6 +33,7 @@ class ExperimentCase(unittest.TestCase): try: exp = cls(self.dbh, scheduler=sched, **kwargs) except KeyError as e: + # skip if ddb does not match requirements raise unittest.SkipTest(*e.args) self.rdb.build() exp.run()