From f5cda3689e36f564a1825828b3706223934981c8 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 2 Jan 2019 16:41:11 +0800 Subject: [PATCH] sayma_amc: enable DRTIO on master SATA connector for MasterDAC variant --- artiq/gateware/targets/sayma_amc.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 499cd55ca..4865203cc 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -279,7 +279,7 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon): ] self.submodules.drtio_transceiver = gth_ultrascale.GTH( clock_pads=self.ad9154_crg.refclk, - data_pads=[platform.request("sfp", i) for i in range(2)], + data_pads=[platform.request("sata")] + [platform.request("sfp", i) for i in range(2)], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") @@ -290,7 +290,7 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon): drtioaux_csr_group = [] drtioaux_memory_group = [] drtio_cri = [] - for i in range(2): + for i in range(3): core_name = "drtio" + str(i) coreaux_name = "drtioaux" + str(i) memory_name = "drtioaux" + str(i) + "_mem"