forked from M-Labs/artiq
sayma_amc: prepare for jesd subclass 1
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@ -6,6 +6,7 @@ from collections import namedtuple
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from migen import *
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.io import DifferentialInput
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from misoc.cores.slave_fpga import SlaveFPGA
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from misoc.cores.slave_fpga import SlaveFPGA
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from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
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from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
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@ -40,6 +41,7 @@ class AD9154CRG(Module, AutoCSR):
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fabric_freq = int(125e6)
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fabric_freq = int(125e6)
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def __init__(self, platform):
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def __init__(self, platform):
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self.jreset = CSRStorage(reset=1)
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self.jreset = CSRStorage(reset=1)
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self.jref = Signal()
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self.refclk = Signal()
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self.refclk = Signal()
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refclk2 = Signal()
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refclk2 = Signal()
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@ -56,6 +58,9 @@ class AD9154CRG(Module, AutoCSR):
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self.cd_jesd.clk.attr.add("keep")
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self.cd_jesd.clk.attr.add("keep")
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platform.add_period_constraint(self.cd_jesd.clk, 1e9/self.refclk_freq)
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platform.add_period_constraint(self.cd_jesd.clk, 1e9/self.refclk_freq)
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jref = platform.request("dac_sysref")
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self.specials += DifferentialInput(jref.p, jref.n, self.jref)
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class AD9154JESD(Module, AutoCSR):
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class AD9154JESD(Module, AutoCSR):
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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@ -86,6 +91,7 @@ class AD9154JESD(Module, AutoCSR):
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phys, settings, converter_data_width=64))
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phys, settings, converter_data_width=64))
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self.submodules.control = control = to_jesd(JESD204BCoreTXControl(core))
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self.submodules.control = control = to_jesd(JESD204BCoreTXControl(core))
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core.register_jsync(platform.request("dac_sync", dac))
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core.register_jsync(platform.request("dac_sync", dac))
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#core.register_jref(jesd_crg.jref) # FIXME: uncomment on next jesd204b update
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class AD9154(Module, AutoCSR):
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class AD9154(Module, AutoCSR):
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