From f33baf339f4bfc891ca4e780580a81bfc5086b70 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 8 Mar 2016 23:34:51 +0100 Subject: [PATCH] pipistrello: drop ttls on pmod, add leds back in --- artiq/gateware/targets/pipistrello.py | 8 +------- doc/manual/core_device.rst | 4 ++-- 2 files changed, 3 insertions(+), 9 deletions(-) diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index e75d9804b..620810b60 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -196,19 +196,13 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4)) - for led_number in range(2): + for led_number in range(4): phy = ttl_simple.Output(platform.request("user_led", led_number)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4)) spi_pins = self.platform.request("pmod_extended_spi", 0) - for i, p in enumerate((spi_pins.int, spi_pins.rst)): - phy = ttl_simple.Inout(p) - self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4, - ofifo_depth=4)) - self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) phy = ttl_simple.ClockGen(platform.request("ttl", 15)) diff --git a/doc/manual/core_device.rst b/doc/manual/core_device.rst index fe3ef2640..484f69358 100644 --- a/doc/manual/core_device.rst +++ b/doc/manual/core_device.rst @@ -128,9 +128,9 @@ When plugged to an adapter, the NIST QC1 hardware can be used. The TTL lines are +--------------+------------+--------------+ | 19 | USER_LED_2 | Output | +--------------+------------+--------------+ -| 20 | PMOD_4 | Input+Output | +| 20 | USER_LED_3 | Output | +--------------+------------+--------------+ -| 21 | PMOD_5 | Input+Output | +| 21 | USER_LED_4 | Output | +--------------+------------+--------------+ | 22 | TTL15 | Clock | +--------------+------------+--------------+