forked from M-Labs/artiq
parent
e7db2c6578
commit
f2632e0fd1
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@ -80,6 +80,8 @@ class SplineParallelDDS(SplineParallelDUC):
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[eqh(x, a.o.a0) for x in self.xi],
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[y.eq(0) for y in self.yi],
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]
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del self.xi
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del self.yi
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class Config(Module):
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@ -157,10 +159,10 @@ class Channel(Module, SatAddMixin):
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self.parallelism = parallelism
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self.cordic_gain = a2.gain*b.gain
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self.u.latency += 1
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b.p.latency += 2
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b.f.latency += 2
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a_latency_delta = hbf[0].latency + b.latency + 2
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self.u.latency += 1 # self.o
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b.p.latency += 1 # self.o
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b.f.latency += 1 # self.o
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a_latency_delta = hbf[0].latency + b.latency + 2 # hbf.i, self.o
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for a in a1, a2:
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a.a.latency += a_latency_delta
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a.p.latency += a_latency_delta
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