forked from M-Labs/artiq
urukul: don't pulse DDS_RST on init
closes m-labs/artiq#940 Apparently, if the DDS are reset, every other time they don't work properly.
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@ -169,7 +169,7 @@ class CPLD:
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Resets the DDS and verifies correct CPLD gateware version.
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"""
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cfg = self.cfg_reg
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self.cfg_reg = cfg | (1 << CFG_RST) | (1 << CFG_IO_RST)
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self.cfg_reg = cfg | (0 << CFG_RST) | (1 << CFG_IO_RST)
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proto_rev = urukul_sta_proto_rev(self.sta_read())
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if proto_rev != STA_PROTO_REV_MATCH:
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raise ValueError("Urukul proto_rev mismatch")
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