From f10c876ed71cf2531626952c0b6fceb8aef773bd Mon Sep 17 00:00:00 2001 From: linuswck <138766547+linuswck@users.noreply.github.com> Date: Thu, 13 Jul 2023 08:37:14 +0000 Subject: [PATCH] kasli-soc: fix GTX initialization The changes are backported from PR2128. Org Problem: DRIO cannot establish connections with satellite after updatting the IBUFDS_GTE2 parameters on commit d6704d30e9380272064b49c1111a29eb1b6afa45. Description of Changes: - CPLL Parameters are added. - CEB signal of IBUFDS_GTE2 is asserted by NOT(OR(stable_clkin, GTX CPLL Locked)). - Modify the GTX Init FSM so that the PLL Reset and GTX Reset are done in two seperated state. - Restart of GTX module now only resets GTX transceiver. --- artiq/gateware/drtio/transceiver/gtx_7series.py | 10 +++++++--- .../gateware/drtio/transceiver/gtx_7series_init.py | 13 +++++++++---- 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/artiq/gateware/drtio/transceiver/gtx_7series.py b/artiq/gateware/drtio/transceiver/gtx_7series.py index e32a8f289..9668e35a3 100644 --- a/artiq/gateware/drtio/transceiver/gtx_7series.py +++ b/artiq/gateware/drtio/transceiver/gtx_7series.py @@ -74,6 +74,8 @@ class GTX_20X(Module): p_CPLL_REFCLK_DIV=1, p_RXOUT_DIV=2, p_TXOUT_DIV=2, + p_CPLL_INIT_CFG=0x00001E, + p_CPLL_LOCK_CFG=0x01C0, i_CPLLRESET=cpllreset, i_CPLLPD=cpllreset, o_CPLLLOCK=cplllock, @@ -290,9 +292,9 @@ class GTX(Module, TransceiverInterface): # # # refclk = Signal() - stable_clkin_n = Signal() + stable_clkin = Signal() self.specials += Instance("IBUFDS_GTE2", - i_CEB=stable_clkin_n, + i_CEB=~stable_clkin, i_I=clock_pads.p, i_IB=clock_pads.n, o_O=refclk, @@ -325,7 +327,6 @@ class GTX(Module, TransceiverInterface): TransceiverInterface.__init__(self, channel_interfaces) for n, gtx in enumerate(self.gtxs): self.comb += [ - stable_clkin_n.eq(~self.stable_clkin.storage), gtx.txenable.eq(self.txenable.storage[n]) ] @@ -334,6 +335,9 @@ class GTX(Module, TransceiverInterface): self.cd_rtio.clk.eq(self.gtxs[master].cd_rtio_tx.clk), self.cd_rtio.rst.eq(reduce(or_, [gtx.cd_rtio_tx.rst for gtx in self.gtxs])) ] + + self.comb += stable_clkin.eq(self.stable_clkin.storage | self.gtxs[0].tx_init.cplllock) + # Connect slave i's `rtio_rx` clock to `rtio_rxi` clock for i in range(nchannels): self.comb += [ diff --git a/artiq/gateware/drtio/transceiver/gtx_7series_init.py b/artiq/gateware/drtio/transceiver/gtx_7series_init.py index 7c2a8ff56..e7dd18887 100644 --- a/artiq/gateware/drtio/transceiver/gtx_7series_init.py +++ b/artiq/gateware/drtio/transceiver/gtx_7series_init.py @@ -108,9 +108,9 @@ class GTXInit(Module): startup_fsm.act("INITIAL", startup_timer.wait.eq(1), - If(startup_timer.done, NextState("RESET_ALL")) + If(startup_timer.done, NextState("RESET_PLL")) ) - startup_fsm.act("RESET_ALL", + startup_fsm.act("RESET_PLL", gtXxreset.eq(1), self.cpllreset.eq(1), pll_reset_timer.wait.eq(1), @@ -118,7 +118,12 @@ class GTXInit(Module): ) startup_fsm.act("RELEASE_PLL_RESET", gtXxreset.eq(1), - If(cplllock, NextState("RELEASE_GTX_RESET")) + If(cplllock, NextState("RESET_GTX")) + ) + startup_fsm.act("RESET_GTX", + gtXxreset.eq(1), + pll_reset_timer.wait.eq(1), + If(pll_reset_timer.done, NextState("RELEASE_GTX_RESET")) ) # Release GTX reset and wait for GTX resetdone # (from UG476, GTX is reset on falling edge @@ -227,7 +232,7 @@ class GTXInit(Module): startup_fsm.act("READY", Xxuserrdy.eq(1), self.done.eq(1), - If(self.restart, NextState("RESET_ALL")) + If(self.restart, NextState("RESET_GTX")) )