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siphaser: support 125 MHz rtio clk 

keep the phase shift increment/decrement at 1/(56*8) rtio_clk
cycles
This commit is contained in:
Robert Jördens 2018-08-29 16:16:37 +00:00
parent ccc58a0f84
commit eb9e9634df
1 changed files with 14 additions and 9 deletions
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17
artiq/gateware/drtio/siphaser.py
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@ -4,17 +4,20 @@ from migen.genlib.cdc import MultiReg
from misoc.interconnect.csr import *
# This code assumes 125/62.5MHz reference clock and 150MHz RTIO frequency.
# This code assumes 125/62.5MHz reference clock and 125MHz or 150MHz RTIO
# frequency.
class SiPhaser7Series(Module, AutoCSR):
def __init__(self, si5324_clkin, si5324_clkout_fabric,
ref_clk=None, ref_div2=False):
ref_clk=None, ref_div2=False, rtio_clk_freq=150e6):
self.switch_clocks = CSRStorage()
self.phase_shift = CSR()
self.phase_shift_done = CSRStatus(reset=1)
self.sample_result = CSRStatus()
# 125MHz/62.5MHz reference clock to 150MHz. VCO @ 750MHz.
assert rtio_clk_freq in (125e6, 150e6)
# 125MHz/62.5MHz reference clock to 125MHz/150MHz. VCO @ 750MHz.
# Used to provide a startup clock to the transceiver through the Si,
# we do not use the crystal reference so that the PFD (f3) frequency
# can be high.
@ -31,10 +34,12 @@ class SiPhaser7Series(Module, AutoCSR):
o_CLKFBOUT=mmcm_freerun_fb, i_CLKFBIN=mmcm_freerun_fb,
p_CLKOUT0_DIVIDE_F=5.0, o_CLKOUT0=mmcm_freerun_output,
p_CLKOUT0_DIVIDE_F=750e6/rtio_clk_freq,
o_CLKOUT0=mmcm_freerun_output,
)
# 150MHz to 150MHz with controllable phase shift, VCO @ 1200MHz.
# 125MHz/150MHz to 125MHz/150MHz with controllable phase shift,
# VCO @ 1000MHz/1200MHz.
# Inserted between CDR and output to Si, used to correct
# non-determinstic skew of Si5324.
mmcm_ps_fb = Signal()
@ -42,7 +47,7 @@ class SiPhaser7Series(Module, AutoCSR):
mmcm_ps_psdone = Signal()
self.specials += \
Instance("MMCME2_ADV",
p_CLKIN1_PERIOD=1e9/150e6,
p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
i_CLKIN1=ClockSignal("rtio_rx0"),
i_RST=ResetSignal("rtio_rx0"),
i_CLKINSEL=1, # yes, 1=CLKIN1 0=CLKIN2