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kasli: add analyzer and RTIO log to DRTIO master target

This commit is contained in:
Sebastien Bourdeauducq 2018-02-27 18:09:07 +08:00
parent 1de2da5644
commit e565d3fa59
1 changed files with 7 additions and 0 deletions
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7
artiq/gateware/targets/kasli.py
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@ -372,6 +372,9 @@ class Master(MiniSoC, AMPSoC):
phy = ttl_simple.Output(platform.request("sfp_ctl", 1).led)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
@ -389,6 +392,10 @@ class Master(MiniSoC, AMPSoC):
[self.rtio_core.cri, self.drtio0.cri])
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.rtio_analyzer = rtio.Analyzer(self.cri_con.switch.slave,
self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
# Never running out of stupid features, GTs on A7 make you pack
# unrelated transceiver PLLs into one GTPE2_COMMON yourself.
def create_qpll(self):