From e565d3fa59a1f5e206186c6ad400c55be48dad0f Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 27 Feb 2018 18:09:07 +0800
Subject: [PATCH] kasli: add analyzer and RTIO log to DRTIO master target

---
 artiq/gateware/targets/kasli.py | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py
index 2ae020e03..9fc71ccde 100755
--- a/artiq/gateware/targets/kasli.py
+++ b/artiq/gateware/targets/kasli.py
@@ -372,6 +372,9 @@ class Master(MiniSoC, AMPSoC):
         phy = ttl_simple.Output(platform.request("sfp_ctl", 1).led)
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy))
+        self.config["HAS_RTIO_LOG"] = None
+        self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
+        rtio_channels.append(rtio.LogChannel())
 
         self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
         self.csr_devices.append("rtio_moninj")
@@ -389,6 +392,10 @@ class Master(MiniSoC, AMPSoC):
             [self.rtio_core.cri, self.drtio0.cri])
         self.register_kernel_cpu_csrdevice("cri_con")
 
+        self.submodules.rtio_analyzer = rtio.Analyzer(self.cri_con.switch.slave,
+                                                      self.get_native_sdram_if())
+        self.csr_devices.append("rtio_analyzer")
+
     # Never running out of stupid features, GTs on A7 make you pack
     # unrelated transceiver PLLs into one GTPE2_COMMON yourself.
     def create_qpll(self):