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drtio: fix FullMemoryWE usage

This commit is contained in:
Sebastien Bourdeauducq 2016-11-23 12:25:43 +08:00
parent 0c49679984
commit e532261a9b
1 changed files with 3 additions and 2 deletions
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5
artiq/gateware/drtio/aux_controller.py
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@ -205,14 +205,15 @@ class Receiver(Module, AutoCSR):
) )
# TODO: FullMemoryWE should be applied by migen.build
@FullMemoryWE()
class AuxController(Module): class AuxController(Module):
def __init__(self, link_layer): def __init__(self, link_layer):
self.bus = wishbone.Interface() self.bus = wishbone.Interface()
self.submodules.transmitter = Transmitter(link_layer, len(self.bus.dat_w)) self.submodules.transmitter = Transmitter(link_layer, len(self.bus.dat_w))
self.submodules.receiver = Receiver(link_layer, len(self.bus.dat_w)) self.submodules.receiver = Receiver(link_layer, len(self.bus.dat_w))
# TODO: FullMemoryWE should be applied by migen.build tx_sdram_if = wishbone.SRAM(self.transmitter.mem, read_only=False)
tx_sdram_if = FullMemoryWE()(wishbone.SRAM(self.transmitter.mem, read_only=False))
rx_sdram_if = wishbone.SRAM(self.receiver.mem, read_only=True) rx_sdram_if = wishbone.SRAM(self.receiver.mem, read_only=True)
wsb = log2_int(len(self.bus.dat_w)//8) wsb = log2_int(len(self.bus.dat_w)//8)
decoder = wishbone.Decoder(self.bus, decoder = wishbone.Decoder(self.bus,