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coredevice: adf5356: fix/adjust docs 

Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
This commit is contained in:
Etienne Wodey 2020-11-09 20:08:33 +01:00 committed by Sébastien Bourdeauducq
parent e8730a7e14
commit dbcac62fd0
3 changed files with 17 additions and 11 deletions
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22
artiq/coredevice/adf5356.py
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@ -32,11 +32,6 @@ SPI_CONFIG = (
ADF5356_MIN_VCO_FREQ = int64(3.4 * GHz) ADF5356_MIN_VCO_FREQ = int64(3.4 * GHz)
ADF5356_MAX_VCO_FREQ = int64(6.8 * GHz) ADF5356_MAX_VCO_FREQ = int64(6.8 * GHz)
ADF5356_MAX_OUTA_FREQ = ADF5356_MAX_VCO_FREQ
ADF5356_MIN_OUTA_FREQ = ADF5356_MIN_VCO_FREQ / 64
ADF5356_MAX_OUTB_FREQ = ADF5356_MAX_VCO_FREQ * 2
ADF5356_MIN_OUTB_FREQ = ADF5356_MIN_VCO_FREQ * 2
ADF5356_MAX_FREQ_PFD = int32(125.0 * MHz) ADF5356_MAX_FREQ_PFD = int32(125.0 * MHz)
ADF5356_MODULUS1 = int32(1 << 24) ADF5356_MODULUS1 = int32(1 << 24)
ADF5356_MAX_MODULUS2 = int32(1 << 28) # FIXME: ADF5356 has 28 bits MOD2 ADF5356_MAX_MODULUS2 = int32(1 << 28) # FIXME: ADF5356 has 28 bits MOD2
@ -114,6 +109,11 @@ class ADF5356:
@kernel @kernel
def read_muxout(self): def read_muxout(self):
"""
Read the state of the MUXOUT line.
By default, this is configured to be the digital lock detection.
"""
return bool(self.cpld.read_reg(0) & (1 << (self.channel + 8))) return bool(self.cpld.read_reg(0) & (1 << (self.channel + 8)))
@kernel @kernel
@ -346,6 +346,9 @@ class ADF5356:
return 1 << ADF5356_REG6_RF_DIVIDER_SELECT_GET(self.regs[6]) return 1 << ADF5356_REG6_RF_DIVIDER_SELECT_GET(self.regs[6])
def info(self): def info(self):
"""
Return a summary of high-level parameters as a dict.
"""
prescaler = ADF5356_REG0_PRESCALER_GET(self.regs[0]) prescaler = ADF5356_REG0_PRESCALER_GET(self.regs[0])
return { return {
# output # output
@ -533,11 +536,14 @@ def calculate_pll(f_vco: TInt64, f_pfd: TInt64):
""" """
Calculate fractional-N PLL parameters such that Calculate fractional-N PLL parameters such that
f_vco = f_pfd * (n + (frac1 + frac2/mod2) / mod1) ``f_vco`` = ``f_pfd`` * (``n`` + (``frac1`` + ``frac2``/``mod2``) / ``mod1``)
where where
mod1 = 2**24 ``mod1 = 2**24`` and ``mod2 <= 2**28``
mod2 = 2**28
:param f_vco: target VCO frequency
:param f_pfd: PFD frequency
:return: ``(n, frac1, (frac2_msb, frac2_lsb), (mod2_msb, mod2_lsb))``
""" """
f_pfd = int64(f_pfd) f_pfd = int64(f_pfd)
f_vco = int64(f_vco) f_vco = int64(f_vco)

2
artiq/coredevice/mirny.py
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@ -38,7 +38,7 @@ class Mirny:
frequency in Hz frequency in Hz
:param clk_sel: Reference clock selection. :param clk_sel: Reference clock selection.
valid options are: 0 - internal 100MHz XO; 1 - front-panel SMA; 2 - valid options are: 0 - internal 100MHz XO; 1 - front-panel SMA; 2 -
internal MMCX internal MMCX
:param core_device: Core device name (default: "core") :param core_device: Core device name (default: "core")
""" """

4
doc/manual/core_drivers_reference.rst
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@ -105,10 +105,10 @@ RF generation drivers
.. automodule:: artiq.coredevice.mirny .. automodule:: artiq.coredevice.mirny
:members: :members:
:mod:`artiq.coredevice.adf5355` module :mod:`artiq.coredevice.adf5356` module
+++++++++++++++++++++++++++++++++++++++ +++++++++++++++++++++++++++++++++++++++
.. automodule:: artiq.coredevice.adf5355 .. automodule:: artiq.coredevice.adf5356
:members: :members:
:mod:`artiq.coredevice.spline` module :mod:`artiq.coredevice.spline` module