occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

comm_cpu: select 64b bus if not kasli v1.x

This commit is contained in:
occheung 2021-11-08 12:36:36 +08:00 committed by Sébastien Bourdeauducq
parent dd68b4ab82
commit d84ad0095b
5 changed files with 27 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
artiq/gateware/targets/kasli.py
View File

@ -104,9 +104,15 @@ class StandaloneBase(MiniSoC, AMPSoC):
}
mem_map.update(MiniSoC.mem_map)
def __init__(self, gateware_identifier_str=None, **kwargs):
def __init__(self, gateware_identifier_str=None, hw_rev="v2.0", **kwargs):
if hw_rev in ("v1.0", "v1.1"):
cpu_bus_width = 32
else:
cpu_bus_width = 64
MiniSoC.__init__(self,
cpu_type="vexriscv",
hw_rev=hw_rev,
cpu_bus_width=cpu_bus_width,
sdram_controller_type="minicon",
l2_size=128*1024,
integrated_sram_size=8192,
@ -255,9 +261,15 @@ class MasterBase(MiniSoC, AMPSoC):
}
mem_map.update(MiniSoC.mem_map)
def __init__(self, rtio_clk_freq=125e6, enable_sata=False, gateware_identifier_str=None, **kwargs):
def __init__(self, rtio_clk_freq=125e6, enable_sata=False, gateware_identifier_str=None, hw_rev="v2.0", **kwargs):
if hw_rev in ("v1.0", "v1.1"):
cpu_bus_width = 32
else:
cpu_bus_width = 64
MiniSoC.__init__(self,
cpu_type="vexriscv",
hw_rev=hw_rev,
cpu_bus_width=cpu_bus_width,
sdram_controller_type="minicon",
l2_size=128*1024,
integrated_sram_size=8192,
@ -431,9 +443,15 @@ class SatelliteBase(BaseSoC):
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, rtio_clk_freq=125e6, enable_sata=False, *, with_wrpll=False, gateware_identifier_str=None, **kwargs):
def __init__(self, rtio_clk_freq=125e6, enable_sata=False, *, with_wrpll=False, gateware_identifier_str=None, hw_rev="v2.0", **kwargs):
if hw_rev in ("v1.0", "v1.1"):
cpu_bus_width = 32
else:
cpu_bus_width = 64
BaseSoC.__init__(self,
cpu_type="vexriscv",
hw_rev=hw_rev,
cpu_bus_width=cpu_bus_width,
sdram_controller_type="minicon",
l2_size=128*1024,
**kwargs)

3
artiq/gateware/targets/kc705.py
View File

@ -132,6 +132,7 @@ class _StandaloneBase(MiniSoC, AMPSoC):
def __init__(self, gateware_identifier_str=None, **kwargs):
MiniSoC.__init__(self,
cpu_type="vexriscv",
cpu_bus_width=64,
sdram_controller_type="minicon",
l2_size=128*1024,
integrated_sram_size=8192,
@ -209,6 +210,7 @@ class _MasterBase(MiniSoC, AMPSoC):
def __init__(self, gateware_identifier_str=None, **kwargs):
MiniSoC.__init__(self,
cpu_type="vexriscv",
cpu_bus_width=64,
sdram_controller_type="minicon",
l2_size=128*1024,
integrated_sram_size=8192,
@ -342,6 +344,7 @@ class _SatelliteBase(BaseSoC):
def __init__(self, gateware_identifier_str=None, sma_as_sat=False, **kwargs):
BaseSoC.__init__(self,
cpu_type="vexriscv",
cpu_bus_width=64,
sdram_controller_type="minicon",
l2_size=128*1024,
integrated_sram_size=8192,

1
artiq/gateware/targets/metlino.py
View File

@ -43,6 +43,7 @@ class Master(MiniSoC, AMPSoC):
def __init__(self, gateware_identifier_str=None, **kwargs):
MiniSoC.__init__(self,
cpu_type="vexriscv",
cpu_bus_width=64,
sdram_controller_type="minicon",
l2_size=128*1024,
integrated_sram_size=8192,

1
artiq/gateware/targets/sayma_amc.py
View File

@ -57,6 +57,7 @@ class SatelliteBase(MiniSoC):
def __init__(self, rtio_clk_freq=125e6, identifier_suffix="", gateware_identifier_str=None, with_sfp=False, *, with_wrpll, **kwargs):
MiniSoC.__init__(self,
cpu_type="vexriscv",
cpu_bus_width=64,
sdram_controller_type="minicon",
l2_size=128*1024,
integrated_sram_size=8192,

1
artiq/gateware/targets/sayma_rtm.py
View File

@ -37,6 +37,7 @@ class _SatelliteBase(BaseSoC):
def __init__(self, rtio_clk_freq, *, with_wrpll, gateware_identifier_str, **kwargs):
BaseSoC.__init__(self,
cpu_type="vexriscv",
cpu_bus_width=64,
**kwargs)
add_identifier(self, gateware_identifier_str=gateware_identifier_str)
self.rtio_clk_freq = rtio_clk_freq