From d4cb1eb998323ad5731659b8180bf04f28501707 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 1 Dec 2016 16:31:00 +0800
Subject: [PATCH] kc705: integrate DMA

---
 artiq/gateware/targets/kc705.py              | 16 +++++++++++-----
 artiq/gateware/targets/kc705_drtio_master.py | 15 ++++++++++-----
 2 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
index 7a9bde597..b06f4753c 100755
--- a/artiq/gateware/targets/kc705.py
+++ b/artiq/gateware/targets/kc705.py
@@ -101,10 +101,11 @@ _ams101_dac = [
 
 class _NIST_Ions(MiniSoC, AMPSoC):
     mem_map = {
-        "timer_kernel":  0x10000000, # (shadow @0x90000000)
-        "rtio":          0x20000000, # (shadow @0xa0000000)
-        "i2c":           0x30000000, # (shadow @0xb0000000)
-        "mailbox":       0x70000000  # (shadow @0xf0000000)
+        "timer_kernel":  0x10000000,
+        "rtio":          0x20000000,
+        "rtio_dma":      0x30000000,
+        "i2c":           0x50000000,
+        "mailbox":       0x70000000
     }
     mem_map.update(MiniSoC.mem_map)
 
@@ -143,8 +144,13 @@ class _NIST_Ions(MiniSoC, AMPSoC):
         self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
         self.csr_devices.append("rtio_crg")
         self.submodules.rtio_core = rtio.Core(rtio_channels)
-        self.submodules.rtio = rtio.KernelInitiator(self.rtio_core.cri)
+        self.submodules.rtio = rtio.KernelInitiator()
+        self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
         self.register_kernel_cpu_csrdevice("rtio")
+        self.register_kernel_cpu_csrdevice("rtio_dma")
+        self.submodules.cri_con = rtio.CRIInterconnectShared(
+            [self.rtio.cri, self.rtio_dma.cri],
+            [self.rtio_core.cri])
         self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
         self.csr_devices.append("rtio_moninj")
 
diff --git a/artiq/gateware/targets/kc705_drtio_master.py b/artiq/gateware/targets/kc705_drtio_master.py
index 5dd5e192a..342ef62bf 100755
--- a/artiq/gateware/targets/kc705_drtio_master.py
+++ b/artiq/gateware/targets/kc705_drtio_master.py
@@ -17,9 +17,10 @@ from artiq import __version__ as artiq_version
 
 class Master(MiniSoC, AMPSoC):
     mem_map = {
-        "timer_kernel":  0x10000000, # (shadow @0x90000000)
-        "rtio":          0x20000000, # (shadow @0xa0000000)
-        "mailbox":       0x70000000  # (shadow @0xf0000000)
+        "timer_kernel":  0x10000000,
+        "rtio":          0x20000000,
+        "rtio_dma":      0x30000000,
+        "mailbox":       0x70000000
     }
     mem_map.update(MiniSoC.mem_map)
 
@@ -56,9 +57,13 @@ class Master(MiniSoC, AMPSoC):
             rtio_channels.append(rtio.Channel.from_phy(phy))
         self.submodules.rtio_core = rtio.Core(rtio_channels, 3)
 
-        self.submodules.cridec = rtio.CRIDecoder([self.drtio.cri, self.rtio_core.cri])
-        self.submodules.rtio = rtio.KernelInitiator(self.cridec.master)
+        self.submodules.rtio = rtio.KernelInitiator()
+        self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
         self.register_kernel_cpu_csrdevice("rtio")
+        self.register_kernel_cpu_csrdevice("rtio_dma")
+        self.submodules.cri_con = rtio.CRIInterconnectShared(
+            [self.rtio.cri, self.rtio_dma.cri],
+            [self.drtio.cri, self.rtio_core.cri])
 
 
 def main():