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siphaser: improve ultrascale clock routing

This commit is contained in:
Sebastien Bourdeauducq 2019-02-25 23:00:01 +08:00
parent de3992bbdd
commit d45249197c
2 changed files with 9 additions and 5 deletions
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11
artiq/gateware/drtio/siphaser.py
View File

@ -9,7 +9,7 @@ from misoc.interconnect.csr import *
class SiPhaser7Series(Module, AutoCSR): class SiPhaser7Series(Module, AutoCSR):
def __init__(self, si5324_clkin, rx_synchronizer, def __init__(self, si5324_clkin, rx_synchronizer,
ref_clk=None, ref_div2=False, rtio_clk_freq=150e6): ref_clk=None, ref_div2=False, ultrascale=False, rtio_clk_freq=150e6):
self.switch_clocks = CSRStorage() self.switch_clocks = CSRStorage()
self.phase_shift = CSR() self.phase_shift = CSR()
self.phase_shift_done = CSRStatus(reset=1) self.phase_shift_done = CSRStatus(reset=1)
@ -22,7 +22,7 @@ class SiPhaser7Series(Module, AutoCSR):
# we do not use the crystal reference so that the PFD (f3) frequency # we do not use the crystal reference so that the PFD (f3) frequency
# can be high. # can be high.
mmcm_freerun_fb = Signal() mmcm_freerun_fb = Signal()
mmcm_freerun_output = Signal() mmcm_freerun_output_raw = Signal()
self.specials += \ self.specials += \
Instance("MMCME2_BASE", Instance("MMCME2_BASE",
p_CLKIN1_PERIOD=16.0 if ref_div2 else 8.0, p_CLKIN1_PERIOD=16.0 if ref_div2 else 8.0,
@ -35,8 +35,13 @@ class SiPhaser7Series(Module, AutoCSR):
o_CLKFBOUT=mmcm_freerun_fb, i_CLKFBIN=mmcm_freerun_fb, o_CLKFBOUT=mmcm_freerun_fb, i_CLKFBIN=mmcm_freerun_fb,
p_CLKOUT0_DIVIDE_F=750e6/rtio_clk_freq, p_CLKOUT0_DIVIDE_F=750e6/rtio_clk_freq,
o_CLKOUT0=mmcm_freerun_output, o_CLKOUT0=mmcm_freerun_output_raw,
) )
if ultrascale:
mmcm_freerun_output = Signal()
self.specials += Instance("BUFG", i_I=mmcm_freerun_output_raw, o_O=mmcm_freerun_output)
else:
mmcm_freerun_output = mmcm_freerun_output_raw
# 125MHz/150MHz to 125MHz/150MHz with controllable phase shift, # 125MHz/150MHz to 125MHz/150MHz with controllable phase shift,
# VCO @ 1000MHz/1200MHz. # VCO @ 1000MHz/1200MHz.

3
artiq/gateware/targets/sayma_amc.py
View File

@ -559,9 +559,8 @@ class Satellite(BaseSoC, RTMCommon):
self.submodules.siphaser = SiPhaser7Series( self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"), si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer, rx_synchronizer=self.rx_synchronizer,
ultrascale=True,
rtio_clk_freq=rtio_clk_freq) rtio_clk_freq=rtio_clk_freq)
platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {mmcm_ps}]",
mmcm_ps=self.siphaser.mmcm_ps_output)
platform.add_false_path_constraints( platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output) self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser") self.csr_devices.append("siphaser")