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wrpll: stabilize DDMTDSamplerGTP

This commit is contained in:
Sebastien Bourdeauducq 2019-12-09 11:47:14 +08:00
parent 0499f83580
commit d43fe644f0
1 changed files with 11 additions and 8 deletions
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19
artiq/gateware/drtio/wrpll/ddmtd.py
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@ -27,20 +27,23 @@ class DDMTDSamplerGTP(Module):
self.rec_clk = Signal() self.rec_clk = Signal()
self.main_xo = Signal() self.main_xo = Signal()
# Getting this signal from IBUFDS_GTE2 is problematic because: # Getting the main XO signal from IBUFDS_GTE2 is problematic because:
# 1. the clock gets divided by 2 # 1. the clock gets divided by 2
# 2. the transceiver PLL craps out if an improper clock signal is applied, # 2. the transceiver PLL craps out if an improper clock signal is applied,
# so we are disabling the buffer until the clock is stable. # so we are disabling the buffer until the clock is stable.
# 3. UG482 says "The O and ODIV2 outputs are not phase matched to each other", # 3. UG482 says "The O and ODIV2 outputs are not phase matched to each other",
# which may or may not be a problem depending on what it actually means. # which may or may not be a problem depending on what it actually means.
main_xo_se = Signal() main_xo_se = Signal()
self.specials += Instance("IBUFDS", self.specials += [
i_I=main_xo_pads.p, i_IB=main_xo_pads.n, Instance("IBUFDS",
o_O=main_xo_se) i_I=main_xo_pads.p, i_IB=main_xo_pads.n,
o_O=main_xo_se),
self.sync.helper += [ Instance("FD", i_C=ClockSignal("helper"),
self.rec_clk.eq(gtp.cd_rtio_rx0.clk), i_D=gtp.cd_rtio_rx0.clk, o_Q=self.rec_clk,
self.main_xo.eq(main_xo_se) attr={("DONT_TOUCH", "TRUE")}),
Instance("FD", i_C=ClockSignal("helper"),
i_D=main_xo_se, o_Q=self.main_xo,
attr={("IOB", "TRUE")}),
] ]