From d3483c1d26ad8049384e656ad773b5637517df52 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 15 Nov 2018 19:40:35 +0800 Subject: [PATCH] kasli: fix SDRAM read delay reset/wrap issue. Closes #1149 --- artiq/firmware/libboard_misoc/sdram.rs | 18 ++++++++++++++++++ conda/artiq-dev/meta.yaml | 2 +- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/artiq/firmware/libboard_misoc/sdram.rs b/artiq/firmware/libboard_misoc/sdram.rs index 0c41e6c0e..6e3071c4b 100644 --- a/artiq/firmware/libboard_misoc/sdram.rs +++ b/artiq/firmware/libboard_misoc/sdram.rs @@ -242,6 +242,12 @@ mod ddr { ddrphy::dly_sel_write(1 << (DQS_SIGNAL_COUNT - n - 1)); ddrphy::rdly_dq_rst_write(1); + #[cfg(soc_platform = "kasli")] + { + for _ in 0..3 { + ddrphy::rdly_dq_bitslip_write(1); + } + } for _ in 0..DDRPHY_MAX_DELAY { let mut working = true; @@ -327,6 +333,12 @@ mod ddr { let mut max_seen_valid = 0; ddrphy::rdly_dq_rst_write(1); + #[cfg(soc_platform = "kasli")] + { + for _ in 0..3 { + ddrphy::rdly_dq_bitslip_write(1); + } + } for delay in 0..DDRPHY_MAX_DELAY { let mut valid = true; @@ -384,6 +396,12 @@ mod ddr { // Set delay to the middle ddrphy::rdly_dq_rst_write(1); + #[cfg(soc_platform = "kasli")] + { + for _ in 0..3 { + ddrphy::rdly_dq_bitslip_write(1); + } + } for _ in 0..mean_delay { ddrphy::rdly_dq_inc_write(1); } diff --git a/conda/artiq-dev/meta.yaml b/conda/artiq-dev/meta.yaml index 48d448b2e..4b596ccd1 100644 --- a/conda/artiq-dev/meta.yaml +++ b/conda/artiq-dev/meta.yaml @@ -15,7 +15,7 @@ requirements: - python >=3.5.3,<3.6 - setuptools 33.1.1 - migen 0.8 py35_0+git2d62c0c - - misoc 0.11 py35_31+git5ce139dd + - misoc 0.11 py35_33+git128750aa - jesd204b 0.10 - microscope - binutils-or1k-linux >=2.27