From d181989de97821e6e242d10c676ea84d27ef8810 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 3 Feb 2017 12:00:58 +0800 Subject: [PATCH] drtio: reset Si5324 at each boot --- artiq/firmware/libboard/si5324.rs | 12 ++++++++++++ artiq/gateware/targets/kc705_drtio_satellite.py | 3 ++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/artiq/firmware/libboard/si5324.rs b/artiq/firmware/libboard/si5324.rs index 597363d19..ff2e44ffb 100644 --- a/artiq/firmware/libboard/si5324.rs +++ b/artiq/firmware/libboard/si5324.rs @@ -1,6 +1,7 @@ use core::result; use i2c; use clock; +use csr; type Result = result::Result; @@ -20,6 +21,12 @@ fn pca9548_select(channel: u8) -> Result<()> { Ok(()) } +fn reset(en: bool) { + unsafe { + csr::si5324_rst_n::out_write(if en { 0 } else { 1 }) + } +} + // NOTE: the logical parameters DO NOT MAP to physical values written // into registers. They have to be mapped; see the datasheet. // DSPLLsim reports the logical parameters in the design summary, not @@ -126,6 +133,11 @@ fn locked() -> Result { pub fn setup_hitless_clock_switching(settings: &FrequencySettings) -> Result<()> { let s = map_frequency_settings(settings)?; + reset(true); + clock::spin_us(1_000); + reset(false); + clock::spin_us(10_000); + #[cfg(soc_platform = "kc705")] pca9548_select(7)?; diff --git a/artiq/gateware/targets/kc705_drtio_satellite.py b/artiq/gateware/targets/kc705_drtio_satellite.py index 2c81db0b4..aff8ff96a 100755 --- a/artiq/gateware/targets/kc705_drtio_satellite.py +++ b/artiq/gateware/targets/kc705_drtio_satellite.py @@ -92,7 +92,8 @@ class Satellite(BaseSoC): i_I=ClockSignal("rtio_rx"), o_O=si5324_clkin.p, o_OB=si5324_clkin.n ) - self.comb += platform.request("si5324").rst_n.eq(1) + self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) + self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c")