sayma_rtm: drive clk_src_ext_sel

2019-12-09 19:47:50 +08:00 · 2019-12-09 19:47:50 +08:00 · d159d0e901
parent b6f7698a69
commit d159d0e901
1 changed files with 2 additions and 0 deletions
--- a/artiq/gateware/targets/sayma_rtm.py
+++ b/artiq/gateware/targets/sayma_rtm.py
@ -185,6 +185,8 @@ class Satellite(_SatelliteBase):

        self.add_rtio(rtio_channels)

+        self.comb += platform.request("clk_src_ext_sel").eq(0)
+
        # HMC clock chip and DAC control
        self.comb += [
            platform.request("ad9154_rst_n", 0).eq(1),